The major trend in electronic products today is to make them smarter, lighter, smaller, thinner, shorter, and faster, while at the same time more friendly, functional, powerful, reliable, robust, innovative, creative, and inexpensive. Different packaging technologies are required for different semiconductor IC devices and application. Two types of advanced electronic packaging using flip chip and µBGA technologies have been studied. This thesis describes the studies of advanced electronic packaging using flip chip and µBGA technologies including (1) Flip chip assembly using anisotropic conductive adhesives (ACF); (2) Flip chip assembly using no-flow underfill; (3) Micro-ball grid array (µBGA) assembly. In chapter 2, flip chip on flex (FCOF) using anisotropic conductive film (ACF) has been demonstrated. Two types of conductive particle in ACF are used in this paper to investigate the effect of pinholes of the electroless nickel bumps on electrical connection of ACF joints of FCOF samples. The conduction mechanisms of both types of ACF joint due to the effect of pinholes have been discussed. After high temperature and high humidity storage, both types of ACF joints show rapid increase in connection resistance at the very beginning of humidity storage. Thereafter, the increasing rate of connection resistance slows down dramatically and finally after long period of humidity storage an almost constant value of connection resistance is achieved. Detail degradation mechanisms for the connection resistance of ACF joints have been proposed. In chapter 3, the correlation between the mechanical strength and the curing condition of no-flow flip chip assemblies using six different reflow profiles has been studied. It is found that both Ni3Sn4 and Cu6Sns intermetallics are formed at the solder/substrate pad and UBM/solder interfaces respectively. The thickness of both IMCs increase with the increasing heating factor. The characteristics of the mechanical strength of these IMCs have been demonstrated. A correlation between the mechanical strength and the interfacial metallurgical reaction has been discussed. Also, the fastest possible reflow profile for both the cure of the underfill and maximizing the shear strength is identified. Based on the observed relationship of the mechanical strength and underfill curing of no-flow flip chip assemblies with Q , the reflow profile should be controlled with caution in order to optimize both the mechanical strength and time for underfill cure. Only a clearer understanding of these correlation can allow manufacturers to develop a optimal, high reliable, low cost, high throughput no-flow flip chip assembly process. In chapter 4, the self-alignment of advanced packages (µBGA) on both non-pinhole and pinhole Au/Ni/Cu pads has been discussed. It is found that a slight reduction of self-alignment of the packages using pinhole pads occurs. RBS results suggest that this reduction should not be attributed to the oxide formation of the surface or interface layer in the Au/Ni/Cu pads. The solder wetting experiments show that slow spreading of molten solder on pinhole pads may result in a reduction of effective board pad surface area that can be wetted. This will reduce the restoring force of the solder joints, and thus causing a less better self-alignment of the packages using pinhole pads. Oxidation of nickel at the exposed area and Au/Ni interface is observed to occur by direct exposure of substrate pads through pinholes during aging. The solder wetting of the aged pads has been described. For flux reflow soldering, the aging of the pads seems to have no serious effect on the self-alignment of the package. However, it is found from the peel-off test that a few solder joints of the samples after reflow have weak adhesion strength at the solder and aged pinhole pad interface. The mechanism for this weak adhesion strength has been proposed. In chapter 5.1, the correlation between Ni3Sn4 intermetallics and Ni3P due to solder reaction assisted crystallization of electroless Ni-P metallization was discussed. Ni3Sn4 intermetallic is formed by the depletion of Ni from electroless Ni-P, and a Ni3P layer is formed simultaneously due to solder reaction-assisted crystallization during solder reflow. Both Ni3Sn4 and Ni3P grow rapidly due to the solder reaction-assisted crystallization and their growths are diffusion controlled during the first 15 minutes of annealing at 220 °C. After that, the growth rate of Ni3Sn4 is greatly reduced and the crystallization of electroless Ni-P to Ni3P is no longer induced. Based on kinetic data and SEM morphology observations, underlying mechanisms causing this specific phenomenon have been proposed. This finding is indeed very crucial since we may control the growth of Ni-Sn intermetallics by monitoring the solder reaction-assisted crystallization of electroless Ni-P. In chapter 5.2, we have studied the metallurgical reaction and mechanical strength of the electroless Ni-P solder joints as a function of reflow time at 220 °C. It is found that both Ni3Sn4 interrnetallics and Ni3P are formed due to the solder reaction-assisted crystallization. However, after the first 15 minutes of reflow, an unusual depression of Ni3Sm growth has been observed. A detailed description of the diffusion mechanism has been presented to explain the prohibition of the Ni3Sn4 growth. It is found that the growth of Ni3Sn4 and Ni3P may have mutual effect on each other during the solder reaction since there is a direct correlation between the depression of the Ni3Sn4 growth and the cease of Ni3P growth. The characteristic of the mechanical strength of electroless Ni-P solder joints has been demonstrated. A correlation between the mechanical strength and the interfacial metallurgical reaction has been discussed. Also, it is found that different reflow time will result in different fracture interfaces of the sheared electroless Ni-P solder joints. The detailed explanation of the fracture surface morphology has been explored. In chapter 6, a nondestructive technique using the Scanning Acoustic Microscopy (SAM) for the standoff height measurement of flip chip assemblies is demonstrated. Flip chip technology is the emerging interconnect technology for the next generation of high performance electronics. One of the important criteria for the reliability issue is the size of the gap between the die and the substrate i.e. standoff height. The method, by means of the implementation of the pulse separation technique, time difference of the representative signals of the die bottom & water interface and water & substrate surface interface from the A-scan image can be found. Then, the corresponding standoff height can be calculated. When comparing this method with the traditional destructive measurement method (SEM analysis on sectioned sample), the results compromise with each other, which suggests that this method yields reliable results.