Scheduling algorithms for input-output buffered packet switching architecture

用於輸入-輸出緩存的分組交換結構的調度算法

Student thesis: Master's Thesis

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Author(s)

  • Sai Po LAM

Related Research Unit(s)

Detail(s)

Awarding Institution
Supervisors/Advisors
Award date30 Jul 1999

    Research areas

  • Packet switching (Data transmission)