Noble metallic nanomaterials for innovative nonvolatile memory devices


Student thesis: Doctoral Thesis

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  • Suting HAN


Awarding Institution
Award date3 Oct 2014


Recently, flash memories have attracted considerable attention as promising next-generation nonvolatile memories owing to its higher chip density, multi-bit per cell storage property and compatibility with the current complementary metal–oxide–semiconductor (CMOS) process. The flash memories based on field-effect transistors (FETs) with floating gate architecture work on the variation of the threshold voltage (Vth) by trapping/detrapping the charge carriers of the semiconductor under external gate bias. This thesis is mainly concerning transistor-based nonvolatile flash memories fabricated on noble metallic nanomaterials floating gates, and proposes solutions based on new materials and new memory structure to improve the device performances of flash memories. Chapter 1 discusses the background and basic concept of nonvolatile memories. In Chapter 2, the organic field-effect transistor (OFET) memory devices with different size of Au nanoparticles (NPs) as charge trapping layers is proposed to achieve reversible Vth shifts and reliable memory performances. We synthesized 15 nm, 20 nm and 25 nm of Au NPs through citrate-reduction method and 3-aminopropyltriethoxysilane (APTES) functionalized substrates has been used to form a monolayer of Au NPs. In the programming/erasing operation, a strong size-dependent effect on Vth shifts and memory effect was observed. For achieving high density charge trapping capability, Chapter 3 demonstrates flexible flash memory based on microcontact printable monolayer of alkanethiol-protected Au NPs array with ultra-high density. Compared with two reference devices with floating gate created by thermal evaporation and electrostatic self-assembly method, largest memory window can be achived. Another important figure of merit for flash memory is the charge retention capability which becomes the main technical hurdle that obstructs the commercialization of flash memories. In Chapter 4, hybrid double floating gate flexible memory device by utilizing rGO sheets monolayer and Au NPs array as upper and lower floating gate were investigated. The rGO can act as buffer layer, charge trapping layer and introduce energy barrier between the Au lower floating gate and channel. The proposed memory devices exhibit strong improvement in both FET and memory characteristics including large memory window and long retention time. In another aspect, it is always a challenge to obtain control over threshold voltage for multimode operation. Chapter 5 demonstrates a flexible floating gate memory device based on chemically doped reduced graphene oxide (rGO) with controlled threshold voltage shifts by proper energy band engineering. In Chapter 6, we demonstrated controllable Vth shifts of transistors based on the Au NPs/P3HT composites. By varying the doping concentration of Au NPs in P3HT matrix, Vth has been tuned from 12 V to 27 V without device degradation. Using this technique, the switching voltages of unipolar inverters have also been systematically tuned. These findings provide a better understanding of electrical properties of flash memories and will be of value for future development of functional electronic memories. These methods can be readily adapted in low cost large area printable electronics.

    Research areas

  • Materials, Nanostructured materials, Precious metals, Flash memories (Computers)