New Product Development Strategies for High-reliability Flexible Electronics Packaging


Student thesis: Doctoral Thesis

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Awarding Institution
Award date18 Jun 2019


Given the high complexity and precision requirements in the development of advanced substrate technologies (full additive process and Electroless Ni/ electroless Pd/ immersion gold (ENEPIG) surface finish) for advanced IC package development, a vast amount of technical challenges are expected prior to mass production. A new approach is needed because of the inability to resolve issues in the conventional manner under industrial time constraints, thereby significantly reducing the competitiveness of high-tech enterprises. This dissertation presents a novel development strategy and its implementation in the new product development (NPD) stage of the state-of-the-art technology in flexible electronics industry. The framework emphasises on risk management and detailed process characterisation for improving product reliability through four distinct stages. The implementation is performed on the basis of critical consideration factors, including product technical characteristics, product lifetime and yield requirement. Starting from the identified new technology, strategic planning is initially conducted to understand and assess the influence of the new product on the enterprise and markets. Subsequently, all possible variables and associated failure modes are mapped out, and the risk level is accurately quantified through a modified failure mode and effect analysis (FMEA), which includes a new variable of product lifetime and an integration of fuzzy logic, to yield precise prioritisation. Such classification of risk level is crucial for reducing the resources for development. Process characterisation is then conducted to resolve the critical risk failures. In this stage, the corresponding critical process parameter and critical quality attribute are discovered, and their relationship is established with a detailed design. In particular, the novelty of the process characterisation provides invaluable scientific contribution on the selected new technologies, resulting in a breakthrough on substrate and interconnect technology. On the novel full additive process, substantial advancement in pitch scalability is achieved through an optimised polyimide surface modification process that produces nano-scale anchoring (PAA layer < 5nm) to minimise moisture uptake despite the layer hydrophilic nature, thereby resolving the adhesion reliability issue on fine-line circuitry. From the advanced assembly technology perspective, plating thickness in ENEPIG tri-layer construction plays a unique and pivotal role to alter the interaction between the material microstructure and resulting bonding process mechanism to yield robust first- and second-level interconnections. For 1st level off-chip interconnection, fine-tuning bonding parameters with a suitable Ni and Pd thickness in Au–Au diffusion bond influences the surface roughness that considerably facilitates the interfacial void shrinkage mechanism to strengthen the metallurgical bond. On the contrary, Pd layer thickness and bonding time in a Cu pillar micro-bump system affect the formation of critical new (Pd, Au) Sn4 IMCs that interrupt the diffusion of Sn, Cu and Ni after bonding. Pd and Au thickness affects the IMC growth mechanism and impacts the formation of stable Ni-containing IMCs for robust joints during extended thermal aging. In terms of board-level interconnection, a reliable Sn–Bi–Ag solder joint by low temperature reflow can be achieved by using a unique combination of Ni and Pd thickness to produce Ni3Sn4 IMC spalling and prevent a thick (Pd, Ni, Bi) Sn4 IMCs formation. With the interaction effect, thin Ni has to be paired with Medium Pd for the most desirable degree of diffusion & IMCs growth throughout the extended reflow. On this basis, the next generation of advanced electronic package is realised through the first demonstration of 8 µm ultra-fine pitch flexible substrate with ENEPIG surface finish for improving interconnect performance reliability. These goals can only be achieved through well-managed and optimised critical variables, thereby exemplifying the importance of process characterisation. Finally, a detailed design guideline with process capability index is established and validated with respect to mechanical, chemical and thermal properties to ensure that the developed product is fully scalable for a robust technology transfer. This study suggests that the framework successfully bridges the gap between new technology invention and product commercialisation by facilitating time-to-market without compromising product lifetime performance. The proposed new substrate technology by integrating full additive process (FAP) and ENEPIG surface metallurgy substantially breakthrough the long standing technology gap of advanced flexible electronics industry.