Modeling of Sectorial Split-Drain Magnetic Field Effect Transistors for Current Sensing Applications

扇形分漏磁敏場效應晶體管的建模及其於電流檢測中的應用

Student thesis: Master's Thesis

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Award date22 Jul 2020

Abstract

Nowadays, there is an increasing demand in smart energy electronics appliances, which operation modes are regulated according to the application, such that to optimize the energy efficiency of the appliances. To accomplish the regulation, the power consumption or loading condition of the system has to be deterministic. Current sensing technique is therefore crucial in the modern electronic systems. For example, light-emitting diode (LED) lighting is an excellent replacement of conventional lighting devices because of the long life-expectancy and low power dissipation of the LED subject to be driven by a constant current driver. A current sensor is able to measure the current flowing through the LED and feedback to the control circuit, such as to generate the appropriate driving condition for the LED. Nonetheless, the current sensor itself consumes energy and the performance of the current regulation is limited by the conversion accuracy of the current sensing element in the current sensor. Current sensing by magnetic induction makes use of a magnetic sensing element which outputs an electronic signal proportional to the magnetic field strength induced by the current flowing in close proximity. Such sensing technique allows completely isolated electrical domain operation and the sensing element itself consumes less power when compared to that of the conventional resistive devices. Therefore, magnetic based current sensor becomes more popular in nowadays current sensing application. Among different magnetic sensing elements, the sectorial split-drain magnetic field-effect transistor (SSD-MAGFET) outperforms other magnetic sensing devices because it is fully CMOS compatible and it has higher sensitivity when compared to other magnetic field-effect transistors in the same silicon area.

To assist the design of the appropriate structure of the SSD-MAGFET, a compact model on the SSD-MAGFET sensitivity is developed in this thesis. With this model, intuitive guidelines on the effects of the devices parameters, such as the sectorial angle, gap width between the two drains, effective aspect ratio, on the operation range and magnetic sensitivity are derived, which is useful for device structure designs and performance optimization.

In previous studies, it was found that the sensitivity of the SSD-MAGFET is geometric dependent and it is sensitive to the channel boundary trapping along the sidewall of the SSD-MAGFET. However, the physical mechanism underneath is not fully exploited. To understand the physics behind the sensitivity behavior of the SSD-MAGFET, three dimensional modeling and numerical simulations based on Silvaco Atlas were conducted in this thesis. The model was calibrated with experimental data obtained from fabricated SSD-MAGFETs in different sector angles. This simulation model can be applied to investigate the movement of the carriers in the SSD-MAGFET subject to the effect of the applied magnetic field as well as provide physical insights into the impact of boundary charge trapping on the magnetic response of the SSD-MAGFET and how such impact affects the design and practical application of this device.

Besides the design on the SSD-MAGFET, the subsequent circuit in converting the sensed signal into an electrical signal for the control circuit is also important. In this thesis, a low cost differential voltage to time conversion method that converts the sensed output of the SSD-MAGFET into a pulse-width modulated (PWM) signal was developed which releases the stringent design requirement and power consumption of sophisticated signal amplification stage and also the tedious output impedance matching for the appropriate biasing of the SSD-MAGFET. The adverse effect of the sensing element and circuit noises are remedied with the introduction of the time integrator in the proposed circuit, and in addition, real time processing is enabled with the digital readout implementation. The performance of the proposed circuit was validated by experiment. The results reveal that this low cost circuit achieves high dynamic range and resolution at low power and complexity.