Investigation on Lanthanum Oxide (La2O3) as Gate Dielectric for Next-Generation CMOS Devices

用於下一代互補式金屬-氧化物-半導體器件的氧化鑭柵介質材料的研究

Student thesis: Doctoral Thesis

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Award date5 Sep 2017

Abstract

To meet the aggressive downsizing to nanoscale in future high-performance complementary metal-oxide-semiconductor (CMOS) devices, rare earth oxides, in particular lanthanum oxide (La2O3), have been increasingly expected to be promising candidates among the next generation of high-k dielectric gate materials, as a replacement of conventional silicon oxide (SiO2). This is because that La2O3 has more attractive advantages in terms of high permittivity (of 27) as well as large energy bandgap (of 5.8 eV) and conduction band offset (of 2.3 eV). In order to achieve smaller equivalent oxide thicknesses (EOT) and more favorable electrical properties, several hot issues on La2O3 gate dielectric films are still waiting further investigation. The main unknowns are associated with the high concentration of oxygen vacancies in the bulk film, the marginally thermal stability with respect to the silicon substrate, and the control of low-k interfacial layer. Recently, a novel gate stacked CeO2/La2O3 structure was proposed by capping a multivalent cerium oxide layer as an oxygen reservoir to control the level of the oxygen vacancies in the bulk La2O3 film. However, the thermal stability, the interfacial properties and the electrical characteristics of La2O3 and CeO2/La2O3 stacked dielectrics are yet to be deeply explored. In this thesis, therefore, has conducted a systematical research work involving the physical characterization and the electrical performance of La2O3 and CeO2/La2O3 gate dielectric films, based on the major issues mentioned above. The specific contributions are highlighted as follow:

First of all, the investigation of the thermal stability and of the interfacial properties of La2O3 material was performed. The interfacial interactions at the La2O3/Si substrate and the La2O3/W gate metal interfaces were discussed through an analysis of the interface bonding structures, as revealed by using angle resolved x-ray photoelectron spectroscopy (ARXPS) measurements.

A detailed depth profiling XPS study was then carried out for this newly proposed CeO2/La2O3 stacked gate dielectrics, based on the chemical bonding structures revealed by the Gaussian decompositions of Ce 3d, La 3d, Si 2s, and O 1s photoemission spectra at different depths. It was found that Ce3+ and Ce4+ states always coexist in the as-deposited CeO2 film. Quantitative analyses were also conducted to study the reduction degree of CeOx with depth. In addition, as compared to the single layer La2O3 sample, the CeO2/La2O3 stack exhibits a larger extent of silicon oxidation at the La2O3/Si interface. This result confirms that the capping CeO2 layer functions as an oxygen supply, which helps to reducing the oxygen vacancies in the film and also suppresses the formation of interfacial La-silicide.

Moreover, the impacts of the thermal annealing on the interface reactions and on the bonding structures of the W/CeO2/La2O3/Si stack were explored in detail. The results indicate that an increasing high-temperature annealing would not only enhance O, Ce, La, and Si diffusion and the intermixing of CeO2/La2O3 stack, but also would facilitate the growth of the interfacial silicate layer at the La2O3/Si interface. The high-temperature annealing would equally result in a significant oxidation of the tungsten film and in the Ce-O-W phases formation at the W/CeO2 interface. A quantitative analysis on the oxidation states of tungsten (i.e., Wn+, with n = 0, 2, 4, 5, and 6) was made by the Gaussian decomposition method. Based on these observations, mechanisms are proposed for the material reactions taking place at both the CeO2/La2O3 stacked films as well as at the W/CeO2-La2O3 and CeO2-La2O3/Si interfaces during the thermal annealing. The influence on the EOT of the growth of the interfacial layers is also discussed.

Furthermore, the electrical properties of MOS capacitors based on La2O3 and CeO2/La2O3 stacked dielectrics were investigated with respect to their capacitance-voltage (C-V) characteristics, the flat band voltages (Vfb) and the trap densities. The results further prove that the proposed CeO2/La2O3 stack is truly effective in compensating the bulk film defects as well as in enhancing both the interfacial properties and the electrical characteristics of La2O3 MOS devices.

The results achieved in this work have the following significant impacts: i) it provides guidelines for achieving smaller EOT gate dielectric film for next-generation Nano-CMOS devices; ii) it reveals the potential of using CeO2 for controlling the amount of oxygen vacancy in La2O3; and iii) it presents detailed analyses on the mechanisms related to thermal stability, interfacial reactions, and defect compensation of high-k materials.