Over the last few decades, the semiconductor industry has gone through many evolutionary changes and breakthroughs to maintain the continuous miniaturization of the device size and the enhancement of operating speed of integrated circuits. According to the recent forecast made by International Technology Roadmap for Semiconductors (ITRS), the IC industry is expanding continuously and the transistor density will soon be over million of transistors per square millimeter for a System-on-Chip (SoC) module. High transistor density and high operating frequency put stringent requirement on the system cooling and packaging and inevitably manifest the power dissipation of SoC. This problem is even tremendous for battery powered systems. Hence, efficient power management systems have to be developed to provide smart power solutions for different applications. The basic working principle of a power management system is to monitor the operating conditions of an electronic system, and to determine an appropriate supply current or voltage for the system. An efficient strategy for power management system is application-dependent and involves every aspect from device to system and even to firmware. In this thesis, some of the important aspects of the emerging smart power management systems will be investigated. Some effective design strategies for power devices as well as some high-performance topologies for the circuit modules used in the power management systems are developed to improve the power efficiency and system reliability. On the device aspect, this work focuses on the design of high voltage capacitors and power MOSFETs with high blocking voltage and low on-resistance. These devices are not only important for high-voltage systems, but also on low-voltage transformer-less systems. In this thesis, the reliability issue of anti-JFET implanted MOSFET which reduces the on-resistance of the device is investigated. Vacuum Dielectric Capacitor (VDC) is ideal for high-voltage applications. In this thesis, power loss characteristic due to leakage current is studied and modeled. A design methodology for minimizing the leakage current is proposed. These results provide useful guidelines for device design and fabrication. Another important reliability issue of the power management systems is the Electrostatic Discharge (ESD). An efficient design of the ESD structure is explored in this thesis. On the circuit aspect, several important circuit modules are developed. A resistorless CMOS bandgap reference for generating sub-1V output voltage is developed for the power regulation circuit applications. One of the important concerns of a MOSFET-based power system is the system latency caused by both the loop delay and the switching delay of a power MOSFET which has large gate capacitance. To alleviate the system latency, a fast response power MOSFET driving circuit is developed to reduce the switching delay of the power MOSFET. The driving circuit uses an operational amplifier with large capacitive drive capability to achieve a faster response. This circuit also reduces the system degradation caused by the switching of the power MOSFET. Meanwhile, a novel D-type flip-flop (DFF) is designed to alleviate the loop latency problem. The DFF is further optimized to consume minimal redundant power and maintains high timing flexibility. These two circuit modules are promising candidates for the low-power and small-latency control modules to be used in the heart of the smart power management systems. This work addresses some important issues of modern power management systems. It makes several useful contributions to the design and fabrication of power devices and circuit modules. Integration of these modules should be application-dependent and requires the detail specifications and requirements of a particular system. It requires tremendous effort for further research and development.