Design of Millimeter-Wave Power Amplifiers in SiGe (Bi) CMOS Technology

基於SiGe (Bi) CMOS工藝的毫米波功率放大器設計

Student thesis: Doctoral Thesis

View graph of relations

Author(s)

Related Research Unit(s)

Detail(s)

Awarding Institution
Supervisors/Advisors
Award date30 Aug 2018

Abstract

As an important spectrum in 5G wireless communications, the millimeter-wave (mm-wave) frequency bands are first applied for next generation mobile communication systems with high data rate and capability of high-integration. The 5G wireless communication technology could support Gb/s data-rate short range communication links and high-resolution video transmitting/receiving. In mm-wave transceiver systems, mm wave power amplifiers (PA) play a key role of output power handling for high frequency signals. However, the implementations of PAs at mm-wave frequency range are still challenging. This dissertation focuses on the design of mm-wave PAs using SiGe (Bi)CMOS technologies.

First, on-chip filtering matching networks (FMN) are presented and designed. These FMNs could be as a single component embedded in mm-wave PAs to provide flexible control of transmission zeros to enhance selectivity of PAs compared with the matching networks that solely use lumped inductors and capacitors. Two mm-wave PAs are designed in 130 nm SiGe (Bi)CMOS technology based on the proposed FMNs. One PA is designed by the single-ended and two-stage architecture at 28 GHz and demonstrates a 22.5 dB gain and about 39.4 % peak power-added efficiency (PAE). Another mm-wave PA is designed using compact filtering impedance networks at the V-band. The measured results reveal a 14.2 dBm saturated output power and 34.9 % peak PAE.

Second, a new topology for on-chip quadrature coupler with wideband performances using a standard 130 nm SiGe (Bi)CMOS technology. This new topology can be used to avoid limitations of metal space in standard (Bi)CMOS technologies and maintain widebandand flat phase response with ultra-low phase differences. The proposed topology utilizes the broadside coupled-line and quarter wavelength transmission lines. To demonstrate the proposed topology, four different types of quadrature couplers have been implemented with broadside coupled-line and lumped-inductors/capacitors in a standard 130 nm SiGe (Bi)CMOS technology. The proposed couplers could operate from 25 GHz to 85 GHz with flat frequency response. The chip size of each proposed quadrature coupler, excluding the testing pads, is only 0.07 mm2.

Furthermore, a fully integrated W-band two-way balanced PA using two quadrature couplers is proposed. This design utilizes the broadside coupled-line and lumped inductors/capacitors to reduce the load-variation sensitivity, which has significant meaning in mm-wave wireless power transmission system that aims to tackle the impedance matching between PA and transmitting antenna. The proposed W-band balanced PA is implemented in a 130 nm SiGe (Bi)CMOS technology and achieves a measured saturated output power Psat of 16.3 dBm and a peak PAE of 14.1% at 100 GHz. The measured Psat with 1-dB bandwidth is from 91 to 102 GHz. The total chip size (with DC pads) is 0.64 mm2 of which the size of the proposed quadrature coupler area is only 0.04 mm2.

Finally, to implement an approach to on-chip self-calibration for mm-wave PA, a novel on-chip mm-wave tunable coupler is proposed for power detection in mm-wave communication system. This on-chip mm-wave 180o coupler with tunable power-dividing ratios use two SiGe varactors. The flat response of power-dividing ratios and phase differences are obtained over a relatively wide frequency band. Theoretical analysis and closed-form design equations are derived for interpretation of the operation principles. For demonstration, a 28-GHz tunable 180o coupler is implemented in 130 nm SiGe (Bi)CMOS technology.