Boundary sampling approximation for VLSI circuit design optimisation

邊際採樣線路反應模擬集成電路最優化之用

Student thesis: Master's Thesis

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Author(s)

  • Kim Tsang CHAN

Related Research Unit(s)

Detail(s)

Awarding Institution
Supervisors/Advisors
Award date30 Jul 1999

Link(s)

Permanent Link https://scholars.cityu.edu.hk/en/theses/theses(dc4d39f0-a23f-4762-bf62-31d06ca4fd6f).html
Other link(s)

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    Research areas

  • Very large scale integration, Integrated circuits, Design and construction