On Flash Read Performance Optimization

Abstract

Nowadays, flash memory-based storage systems are widely used in mobile phones, personal computers and other systems. Although the flash memory has the advantages of shock resistance, non-volatility and high access performance, its cost is still high, which hinders the use of full-flash memory systems. In order to reduce market costs, a large number of high-density flash memories are studied and developed, such as triple-level per cell (TLC) flash memory and 3D NAND flash memory. This, however, causes worse data reliability in current flash memory systems.

In order to relieve reliability problem caused by technology scaling, LDPC codes have been widely applied in flash memories to provide high error correction capability. However, the increased error correction capability has to trade with high read latency, which largely decreases read performance of flash memory systems. This thesis proposes three novel techniques to optimize this problem, listed as follows.

1. Exploiting data read characteristics, LDR, a lightweight data refresh method is proposed, which aggressively corrects errors in read-hot pages that requires high read levels and reprograms error-free data into new pages. LDR contains two techniques: read-hot page identification and lightweight page refresh. The first technique applies a decision tree to decide which pages should be refreshed while the second technique establishes several refresh queues for flash packages and invokes the refresh operations. Experimental results show that LDR can achieve 29% read performance improvement with only 0.2% extra P/E cycles on average, which causes negligible overhead on flash lifetime.

2. Latency-aware LDPC (LaLDPC) is proposed to remove redundant read-retry steps involved in current iterative LDPC read process. Firstly, read level characteristics along with data retention is studied. From the results, it is observed that a single read level stays appropriate for a long time, which is called the temporal read level locality. Using this characteristic, LaLDPC estimates the appropriate read level for each page and stores it in the flash translation layer. As an example, it is shown that how to integrate LaLDPC into the Demand-based Flash Translation Layer (DFTL). Besides, in order to further strengthen the capability of LaLDPC based on DFTL, a new cache eviction algorithm is also proposed to leave entries with high read levels in the cache as long as possible. Experimental results show that LaLDPC saves 56% of read retries and improves SSD read performance by 18% on average compared with the current LDPC method.

3. To balance performance and reliability, a new garbage collection method integrated with a selective LDPC read method is proposed and named as LDPC-aware Garbage Collection (LaGC), to choose blocks with high error rates to perform LDPC reads on these blocks but direct reads on other blocks. In this way, the high error rates can be controlled not to become bad blocks. Besides, these blocks are often close to uncorrectable error rates, which take a small portion during a long flash life period. Thus, most of blocks do not perform LDPC reads and keep the advantage of low read latency. Experimental results show that LaGC can reduce 78% of read latency in traditional GC method and achieve about 2% system performance improvement.

In summary, by analyzing the LDPC read process in flash memory system, the above methods are proposed from two aspects: local optimization and global optimization. The first innovation focuses on optimizing the flash memory sensing steps, in which high latencies are involved, belonging to local optimization. The second and third innovations focus on optimizing the mechanism used throughout the read process and are globally optimized.

Date of Award	22 Dec 2017
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Chun Jason XUE (Supervisor) & Deqing Zou (External Supervisor)