Memory optimizations for high performance low power embedded systems

Abstract

With the wide application of embedded systems in consumer, industrial, medical and military areas nowadays, memory design has become a bottleneck in system performance and power consumption. Traditionally, cache memory is fabricated from pure SRAM. Targeting the embedded system architecture with a SRAM-based cache, this thesis exploits the cache locking technique to offer a high performance cache design. As technology develops rapidly, conventional SRAM-based caches are facing severe challenges of large leakage power and large cell size. Recent developments of non-volatile memories (NVMs), such as Spin-Transfer Torque RAM (STT-RAM) and Phase Change Memory (PCM), indicating characteristics of low leakage power and high storage density have shown that they are qualified candidates for building memories in embedded systems. However, these NVMs suffer longer latency and higher power consumption on write operations than SRAM. Addressing the critical issues of NVMs and considering loops in embedded applications, this thesis exploits loop transformation techniques to save dynamic energy for NVMs-based memories. In particular, this thesis consists of the following four topics. • A dynamic instruction cache locking method is presented to improve instruction cache performance and save power consumption. • A data re-allocation enabled cache locking method is presented to improve data cache performance. • A migration-aware loop retiming method is presented to save power consumption for STT-RAM/SRAM-based hybrid caches. • A write mode aware loop tiling method is presented to improve performance and save power consumption for PCM-based main memory. The first two topics focus on the cache locking technique to achieve high performance for traditional SRAM-based caches. The last two topics focus on the loop transforming technique to achieve low energy for the NVMs-based caches and main memory.

Date of Award	15 Jul 2014
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Chun Jason XUE (Supervisor)