Efficient Hardware Accelerations for Post-Quantum Cryptography in the IoT Domain

Abstract

Quantum computers are in a stage of rapid development. However, quantum computing poses a huge threat to the traditional public key encryption algorithm system because it can solve the discrete logarithm problem in polynomial time. This ability undermines the security of traditional public key algorithms. To tackle this issue, the National Institute of Standards and Technology (NIST) in the United States has initiated several competitions aimed at developing Post-Quantum Cryptography (PQC). However, these algorithms often exhibit long running time and storage requirements, making them unsuitable for resource-constrained Internet of Things (IoT) devices. The key challenge for hardware acceleration schemes in post-quantum cryptography targeting IoT platforms is to achieve algorithm acceleration while minimizing resource usage and cost overheads. This thesis explores hardware acceleration solutions for lattice-based and hash-based post-quantum cryptography, with a focus on enhancing the efficiency of IoT devices while reducing hardware power consumption and area overheads.

First, a Number Theoretic Transformation (NTT) accelerator (PipeNTT) is designed, which plays a crucial role in post-quantum cryptography. This research focuses on developing optimized algorithms and hardware units for specific modular operations, along with data flow optimizations at the computational level. The proposed architecture includes a pipelined hardware NTT accelerator that improves the critical NTT operation while balancing performance and area efficiency.

Second, a RISC-V instruction set extension is specifically designed to enhance hash-based post-quantum cryptography. This custom instruction set improves the RISC-V architecture by accelerating hash function operations and optimizing hash-based post-quantum cryptography algorithms at the software level. Additionally, this design offers flexibility for future extensions, supporting all operations of hash-based PQC algorithms. As a result, it achieves high run-time efficiency and low power consumption, making it well-suited for IoT applications.

Third, based on the design ideas and research methods of PipeNTT, the above-mentioned RISC-V custom instruction set processor RVSLH is further modified and optimized to support the acceleration of lattice-based post-quantum cryptography schemes. It optimizes key operations through resource sharing, operation aggregation, software and hardware co-design, and parallel computing. The design comprehensively supports all operations necessary for lattice-based PQC. It strikes a balance between resource usage and power consumption while providing effective hardware acceleration.

Finally, the above RISC-V instruction set is expanded to support the hardware acceleration of NTRU lattice-based PQC schemes. Alongside this expansion, a System-On-Chip (SoC) architecture is proposed. Enhancements to the above RISC-V instruction set are made by analyzing the characteristics of NTRU lattice-based PQC. Additionally, an automated dual-issue hardware tool is designed to support these NTRU lattice-based post-quantum cryptography algorithms. This proposal provides a comprehensive SoC architecture design, creating an efficient hardware platform for implementing post-quantum cryptography algorithms on IoT devices. Through these studies, a unified PQC processor and system-on-chip that can simultaneously support hash-based, lattice-based, and NTRU-based PQC is realized.

To summarize, this thesis investigates hardware acceleration and optimization techniques for hash-based and lattice-based post-quantum cryptography specifically designed for IoT platforms. The main goal is to enhance the execution efficiency of these algorithms while reducing hardware area, power consumption, and resource overhead. The study implements various optimizations by analyzing PQC algorithms, including parallel computing, data flow optimization, resource reuse, and operational optimization. Comprehensive testing and evaluation are conducted on both FPGA and ASIC platforms, clearly demonstrating the advantages of our designs for IoT applications and improving the efficiency of executing post-quantum cryptographic algorithms on the developed platform.

Date of Award	15 Jul 2025
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Chak Chung Ray CHEUNG (Supervisor) & Kejie HUANG (External Supervisor)