Design of High Efficiency Microwave Power Amplifier and Oscillator Using CMOS Technology

Abstract

With wireless communication moving from the 4rd to the 5th generation and beyond, mobile equipment with a high data rate, low cost and full integration will be in great need. The millimeter-wave frequency is supposed to expand the future of wireless communication due to its characteristics such as the possibility of a multi-Gbps data rate, low interference and minimum time delay. The Complementary Metal-Oxide-Semiconductor (CMOS) technology features low cost, low power consumption and high integration. With a scaled fabrication process, it has been proven to be capable of offering promising RF performance comparable to that of III-V technology. As a result, there is increasing interest in using CMOS technology to realize transceiver building blocks such as power amplifiers (PAs) and voltage-controlled oscillators (VCOs). Nevertheless, due to CMOS device limitations such as a low cut-off frequency and high parasitic capacitance, the circuit performance of the millimeter-wave is limited.
This dissertation focuses on the design of high efficiency microwave PAs and VCOs using CMOS technology.
First, a novel multi-section coupled lines (MSCL) matching network is proposed. The impedance transformation of the proposed two-port matching network is realized in a single structure. It is suitable for a millimeter-wave CMOS-integrated circuit design because the proposed matching network owns a high quality factor compared with traditional transformer or inductor-based matching networks. It provides an inherent DC-block function and is compact in size compared with the transmission line based matching network. Two millimeter-wave power amplifiers are designed in 65 nm CMOS based on the proposed matching network. One amplifier is designed with a differential architecture at 60 GHz and demonstrates a 20 dB gain and a more than 15 GHz bandwidth. Another is designed using a power-combined technique with gain roll-off compensation and achieves 20 dB gain at the V-band. The large signal measurement reveals 15 dBm saturated output power and 15.5% peak PAE.
Second, a novel Doherty power amplifier PA with enhanced back-off efficiency is proposed. To achieve the Doherty operation at 60 GHz using CMOS technology, a dual adaptive biasing scheme is applied. It enables the carrier and peaking amplifier to work at their optimized biasing condition according to the input power levels. The coordination of the load modulation network and the adaptive bias technique eliminate the back-off efficiency degradation caused by the peaking amplifier at a low power level. Moreover, as the proposed Doherty PA avoids using any λ/4 impedance transformers, the chip size is reduced. The designed PA is fabricated and experimentally verified. It reveals a 16 dBm maximum output power with 17.5% PAE. An approximately 9% PAE at an 8 dB back-off power level is demonstrated.
Furthermore, a fully integrated direct combining power amplifier is presented at 60 GHz. An adaptive biasing technique is employed to shut down the auxiliary PA at a low power level for back-off efficiency enhancement. When it is in high-power operation, the circuit provides optimum bias voltages to the auxiliary PA, leading to highly efficient power combining. The load modulation network is built based on transmission lines and transformers. Optimum load impedances are offered for both PAs at designed power levels. Adaptive input power dividing technique is also utilized. It minimizes the gain drop at low power levels by delivering more power to the main PA while equally distributing the input signal to both PAs for highly efficient power combining at a high power level. The measurement reveals a 16.5 dBm maximum output power and 14% peak PAE. An 8% PAE at a 6 dB back-off is exhibited.
Finally, RF and THz VCOs with high oscillation efficiency are investigated in this dissertation. A wideband and low phase noise quadrature VCO (QVCO) is designed in 0.18 μm CMOS. To reduce the phase noise while providing high oscillation efficiency, the Class-C biased bulk-coupled topology is employed in a PMOS-only VCO. Significant phase noise improvement is achieved based on the measurement. A wide tuning range is realized by a 4-bit switchable cap-array ranging from 5.6 GHz to 6.9 GHz. The quadrature accuracy of the proposed QVCO is evaluated based on an image-rejection mixer (IR-mixer), which exhibits a peak image rejection ratio (IRR) of 40 dBc, indicating low amplitude and phase errors simultaneously. In addition, a push-push VCO working at 0.2 THz is explored. A capacitance-splitting technique is applied in the design by employing a pair of inductors between the gate and drain of the cross coupled transistors. Using the applied technique, the required transistor size is reduced while the phase noise and oscillation efficiency are improved. The VCO performance is experimentally verified.
The measured output power is -13.7 dBm, consuming a 10 mA DC current under a 1.2 V power supply, indicating a high efficiency of 3.5‰ for THz generation.

Date of Award	18 Mar 2016
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Quan XUE (Supervisor)