Configurable architectures for mixed high precision floating point arithmetic

Abstract

Floating point arithmetic is widely used in many scientific and engineering computations, numerical and signal processing applications. Its huge dynamic range and convenient scaling of the number range provides a convenient platform for designers to realize their algorithms. However, implementing arithmetic operations for floating point numbers in hardware is very challenging. Also, due to increasing demand of more high precision arithmetic, IEEE-754 floating point standard has defined and incorporated the quadruple precision (128-bit) format, in 2008. Field Programmable Gate Array (FPGA) are becoming a major competitor for the high performance computing machines, and even current era Super-Computers are using the FPGAs to off-load and accelerate the parallelizable complex routines over them. Since last 2-3 decades, FPGAs are potentially researched and adopted for a large set of floating point related applications. A significant range of literature are focused on the design of efficient floating point arithmetic implementations for the FPGA platforms. Despite several advancement and many implementation strategies, the area requirements and performance numbers of these arithmetic computations are appears as a main bottleneck, specially when size increases (from single precision to quadruple precision). In view of above, a part of the current research work is aimed for the high performance and area efficient architectures for floating point arithmetic, specially for double and quadruple precision format, on FPGAs platforms, which can be easily extended for ASIC synthesis platform. In this thesis, FPGA based architectures for double and quadruple (high) precision multiplication and division arithmetic are proposed, which out-perform the best available literature works, in terms of area, speed and latency. A significant portion of this thesis is focused on the development of standard cell based ASIC (Application Specific Integrated Circuit) architectures for "dynamically configurable multi-mode multi-precision (mixed) floating point arithmetic". Based on the IEEE-754 standard formats, three categories of configurable multi-mode multi-precision architectures, for basic arithmetic (adder/subtractor, multiplier and division), are developed as: (Dual-mode) Double Precision with dual (two-parallel) Single Precision (DPdSP) Arithmetic Architecture; (Dual-mode) Quadruple Precision with dual (twoparallel) Double Precision (QPdDP) Arithmetic Architecture; and (Tri-mode) Quadruple Precision with dual (two-parallel) Double Precision, quad (four-parallel) Single Precision (QPdDPqSP) Arithmetic Architecture. These architectures aim towards a unified multi-mode multi-precision architecture, for better resource utilization. These proposed architectures, designed for high precision computation, can be dynamically configured for multiple lower precision computations. These proposed architectures support normal as well as sub-normal computations. Literature contains very limited work on this area, and mainly talks for dual-mode architectures, with only normal support. The proposed dual-mode architectures, for each targeted arithmetic, show a significant benefit over existing dual-mode works, whereas the tri-mode architectures stands among fresh proposals. These multi-mode arithmetic architectures are further combined to form multi-mode multi-precision floating point arithmetic unit (FPU). This thesis, currently, aimed for the mixed high precision arithmetic architectures for the standard IEEE-754 formats, however, it can be easily extended for any custom precision arithmetic architecture.

Date of Award	3 Oct 2014
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Chak Chung Ray CHEUNG (Supervisor)