Characterization and modeling of the switching behavior of power MOSFET in power electronic systems

Abstract

Power semiconductor devices are the soul of power electronic systems, among which, the power MOSFET distinguishes itself upon the center stage of high-frequency and medium/low power applications. With rapid increase in the switching frequencies of power converters, the parasitic elements in both the circuit and the power MOSFET itself exert more and more significant influence on the switching performance of the power MOSFET. There are two typical configurations in which the power MOSFET operates in the power electronic systems: one is the MOSFET-diode configuration, the other is the bridge-leg configuration. This thesis focuses on establishing a detailed analytical model for the switching behavior of the power MOSFET in these two configurations. It considers all crucial parasitic elements and the interaction between the gate drive stage and the power stage. A more insightful understanding of the switching characteristics of the power MOSFET can thereby be acquired. Snubber circuit is often adopted in the switch-diode configuration to alleviate the voltage stress across the switching device. Existing design for the switch-snubber-diode configuration is conducted by separately considering the switch and the snubber circuit, while in fact they can interact with each other. To optimize the circuit design in terms of power losses and voltage stress, the effect of the gate drive resistance on the losses of the MOSFET–snubber–diode configuration will be investigated. The concept of optimal gate drive resistance in such a configuration will thereby be proposed. With the increase in the switching speed and power level in the bridge-leg configuration, the spurious triggering pulse in the synchronous switch is liable to exceed the threshold voltage and cause spurious turn-on. Eliminating the spurious turn-on plays an important role in preventing excessive switching losses, circuit oscillation and shootthrough. In this thesis, this problem will be tackled from two aspects based on the synchronous buck converter with power MOSFETs as the switching devices. On the one hand, the magnitude of the spurious triggering pulse should be minimized by optimized circuit design. In this light, the mechanism and contributing factors of the spurious triggering pulse will be clarified by an elaborate model of the switching transition when the pulse turns up. On the other hand, a novel RCD level-shifter circuit will be proposed to shift the spurious triggering pulse below the threshold voltage to avoid spurious turn-on. The work of this thesis can help identify the most influential factors on the switching characteristics of the power MOSFET, and cast light on the characterization of other switching devices, such as IGBT. Accordingly, circuit designers can make targeted decisions in component selection, PCB layout and trouble-shooting; process and package engineers can interpret the expectations on the circuit-level performance of the power MOSFET into the requirements on its parameters, and optimize the physical-level and the package design of the power MOSFET.

Date of Award	15 Jul 2014
Original language	English
Awarding Institution	City University of Hong Kong
Supervisor	Shu Hung Henry CHUNG (Supervisor)