Automated intelligent inspection strategy for surface mounted board

Abstract

Verification of error in SMB manufacturing still relies heavily on human visual inspection. With high density, small chip size and high complexity of the surface mount board, an automated intelligent inspection system is necessary to minimize manufacturing mistakes. Most importantly, the system must be capable of linking errors to their causes in the manufacturing process, so that corrective actions can be taken immediately. The common faults in SMB manufacturing are missing chips, correctness of chips, orientation and alignment of chips, and quality of solder joints. In this dissertation, a robust intelligent vision system architecture and several algorithms are developed to tackle this demanding and challenging problem. Due to the lack of an industrial standard, different marking schemes appear on the same chip from different manufacturers, and for a given manufacturer, different formats are used on different packages. The problems of printing quality, location variation and format inconsistency coupled with handling in the manufacturing process cause the chip image quality to be less than ideal. The emphasis of high speed at the expense of resolution makes character recognition and dimensional measurement extremely difficult. In addition, the solder joint visual images captured under the poor resolution and varying lighting conditions are insufficient in details which are necessary for fault classification. To verify the chip at high speed, the whole chip image is captured and processed at a time. Different algorithms are developed to deal with resolution difference among various chip sizes that can have a factor of 10-15. To overcome image imperfection and for accurate chip identification, a chip reference database is established. Information on the board under test and its chips is directly downloaded to the vision system. A comprehensive graphical user interface with the electronic device and checking board database storage system is created for easy access and update of information. To deal with varying character and symbol sizes, an iterative sampling method is used to separate characters and symbols from the background and subsequently bounded by a rectangular array. The array is then enlarged or reduced into a 10x10 array as the input to the recognition process. To improve the recognition rate and be adaptive to the actual illumination environment, an Artificial Neural Network (ANN) is suggested. Three types of neural network with different network settings are tested. A classification rate of 85 - 90% has been achieved. To further enhance the performance, a chip information filtering system is added to the ANN. The filtering rules are easy to generate and maintain. To check the precision alignment and orientation correctness of a chip on the SMB, a sampling measurement methodology applied towards the outline pixels of the chip is implemented. This method is tested and provides satisfactory accuracy in measurement. The solder joint fault recognition and classification represent the biggest effort and contribution of this research work. Through the systematic analysis of results, a new solder joint fault representation scheme tailored as ANN input is developed. With the aid of ANN, faults are identified, classified and successively linked to the related steps in the manufacturing process. The robustness and tolerance of the recognition are discussed.

Date of Award	18 Oct 1996
Original language	English
Awarding Institution	City University of Hong Kong