Abstract
Power electronic systems are already part of life and are important for generating, storing, and distributing electrical energy. The bridge leg configuration is a fundamental topology in power electronic systems. It is formed by two series connected switching devices switching alternately. However, due to the parasitic components within the circuit, crosstalk is introduced on the synchronous switch during the switching transient of the control switch, and vice versa, which may cause a false triggering and shoot-through.Currently, Silicon (Si) MOSFET or Insulated Gate Bipolar Transistor (IGBT) are widely used. However, the Si devices have reached their physical limitations. Recently, Silicon Carbide (SiC) MOSFETs have been introduced, offering superior performance characteristics such as lower power losses, higher switching frequencies, and high voltage and temperature operations capabilities.
Despite these advantages, SiC MOSFETs in bridge leg configurations face three primary issues: firstly, the higher magnitude of crosstalk due to increased switching speeds and lower maximum allowable negative gate voltages exacerbates false triggering and gate breakdown concerns. Secondly, the variability in on-state resistance and body diode forward voltage presents operational challenges. Lastly, these devices are subject to reliability concerns due to the manufacturing process and the harsh operating conditions.
Although the superior performance of SiC MOSFET makes them an alternative to Si MOSFET, maximizing their benefits requires specialized solutions. First are the multilevel gate drivers for temporarily generating a negative voltage to counteract the positive spurious voltage and back to zero to suppress the negative spurious voltages and reduce power loss. Additionally, it is critical to have monitoring circuits to tracking device degradation to ensure safety, thereby addressing the reliability issues inherent to SiC MOSFETs in practical applications.
This thesis presents advanced gate-driving topologies for providing multi-level gate driving at a low cost or integrating the functionality of online condition monitoring in the converter.
Firstly, a passive resonant level shifter has been proposed. The circuit can suppress the effect of the crosstalk and deliver a low off-state gate-source voltage to reduce the forward voltage drop of the body diode of SiC MOSFETs. The circuit only comprises eight passive components, so it is simple, cost-effective, and reliable. The circuit is composed of two parts. The first one is a series resonant tank circuit. It generates short voltage pulses to counteract the voltage pulses caused by the crosstalk and return to zero during steady state. The second one is a resistor-capacitor-diode (RCD) level shifter that delivers a static negative off-state gate-source voltage to the MOSFETs. The static voltage level is designed to be close to zero, so that the forward voltage drop of the body diode is lowered.
Secondly, an adaptive gate driver has been proposed. The circuit can regulate the off-state gate-source voltage according to the spurious voltage caused by the crosstalk effect and maintain low gate-source voltage during off-state. A holistic assessment of the changes in major intrinsic parameters before and after aging SiC MOSFETs with repetitive short-circuit tests is given. Gate leakage is found to be an appropriate precursor to reflect gate oxide degradation. The proposed circuit utilizies this phenomenon to monitor the health condition of the switch indirectly by observing the load effect of gate leakage on voltage level change without imposing additional cost on the overall hardware implementation. Apart from resolving the crosstalk issue, an optimal off-state gate-source voltage can also improve the life expectancy of the switching device.
Lastly, a gate driver has been proposed that uses a single power supply to generate a negative off-state gate source voltage and dynamically regulate this voltage to counteract spurious voltage pulses caused by crosstalk to minimize the gate-oxide stress. It preserves the on-state gate-source voltage, avoiding increased conduction losses. Additionally, the driver monitors gate-source leakage current and source inductance, enabling reliable detection of gate oxide degradation and bond wire liftoff. These monitoring results are largely independent of duty cycle and temperature, ensuring consistent performance across operating conditions.
| Date of Award | 21 May 2025 |
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| Original language | English |
| Awarding Institution |
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| Supervisor | Shu Hung Henry CHUNG (Supervisor) & Wing Hong Ricky LAU (Supervisor) |