Z-TCAM : An SRAM-based architecture for TCAM

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Original languageEnglish
Article number6774983
Pages (from-to)402-406
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number2
Online published18 Mar 2014
Publication statusPublished - Feb 2015


Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave like TCAM? This brief proposes a novel memory architecture, named Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM subtables, which are then processed to map on their corresponding memory blocks. Two example designs for Z-TCAM of sizes 512 × 36 and 64 × 32 have been implemented on Xilinx Virtex-7 field-programmable gate array. The design of 64 × 32 Z-TCAM has also been implemented using OSUcells library for 0.18 μm technology, which confirms the physical and technical feasibility of Z-TCAM. Search latency for each design is three clock cycles. The detailed implementation results and power measurements for each design have been reported thoroughly.

Research Area(s)

  • Application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), memory architecture, priority encoder, static random access memory (SRAM)-based TCAM, ternary content addressable memory (TCAM).