ZnO Nanofiber Thin-Film Transistors with Low-Operating Voltages

Although significant progress has been made towards using ZnO nanofibers (NFs) in future high-performance and low-cost electronics, they still suffer from insufficient device performance caused by substantial surface roughness (i.e., irregularity) and granular structure of the obtained NFs. Here, a simple one-step electrospinning process (i.e., without hot-press) is presented to obtain controllable ZnO NF networks to achieve high-performance, large-scale, and low-operating-power thin-film transistors. By precisely manipulating annealing temperature during NF fabrication, their crystallinity, grain size distribution, surface morphology, and corresponding device performance can be regulated reliably for enhanced transistor performances. For the optimal annealing temperature of 500 °C, the device exhibits impressive electrical characteristics, including a small positive threshold voltage (V_th) of ≈0.9 V, a low leakage current of ≈10⁻¹² A, and a superior on/off current ratio of ≈10⁶, corresponding to one of the best-performed ZnO NF devices reported to date. When high-κ AlO_x thin films are employed as gate dielectrics, the source/drain voltage (V_DS) can be substantially reduced by 10× to a range of only 0–3 V, along with a 10× improvement in mobility to a respectable value of 0.2 cm² V⁻¹ s⁻¹. These results indicate the potential of these nanofibers for use in next-generation low-power devices.