TY - JOUR
T1 - Zero-Order Switching Networks and Their Applications to Power Factor Correction in Switching Converters
AU - Tse, Chi K.
PY - 1997/8
Y1 - 1997/8
N2 - This paper addresses the requirements of networks containing linear inductors, capacitors and ideal switches for synthesis of zero-order input impedance. Sufficient conditions for achieving zero-order input impedance are stated in terms of the network topology and the switching sequence. Such networks have direct practical relevance to power factor correction (PFC). Based on zero-order switching networks, a comprehensive study is presented for many existing PFC circuits as well as new circuit topologies. © 1997 IEEE.
AB - This paper addresses the requirements of networks containing linear inductors, capacitors and ideal switches for synthesis of zero-order input impedance. Sufficient conditions for achieving zero-order input impedance are stated in terms of the network topology and the switching sequence. Such networks have direct practical relevance to power factor correction (PFC). Based on zero-order switching networks, a comprehensive study is presented for many existing PFC circuits as well as new circuit topologies. © 1997 IEEE.
KW - DC/DC converters
KW - Graph theory applications
KW - Power factor correction
KW - Switch mode power supplies
UR - http://www.scopus.com/inward/record.url?scp=0031199837&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0031199837&origin=recordpage
U2 - 10.1109/81.611261
DO - 10.1109/81.611261
M3 - RGC 21 - Publication in refereed journal
SN - 1057-7122
VL - 44
SP - 667
EP - 675
JO - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
JF - IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
IS - 8
ER -