Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

2 Scopus Citations
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Detail(s)

Original languageEnglish
Article number7273842
Pages (from-to)2313-2324
Journal / PublicationIEEE Transactions on Computers
Volume65
Issue number7
Publication statusPublished - 1 Jul 2016

Abstract

Architecting PCM, especially MLC PCM, as main memory for MCUs is a promising technique to replace conventional DRAM deployment. However, PCM/MLC PCM suffers from long write latency and large write energy. Recent work has proposed a compiler directed dual-write (CDDW) scheme to combat the drawbacks of PCM by adopting fast or slow mode for different write operations. For large-scale loops, we observe that write instances' lifetime is very long and can only be written by the expensive slow mode. This paper proposes a write mode aware loop tiling approach to effectively reduce the lifetime of write instances and maximize the number of efficient fast writes in loops. The experimental results show that the proposed approach improves performance by 50.8 percent and reduces dynamic energy by 32.0 percent across a set of benchmarks compared to the CDDW approach on average.

Research Area(s)

  • embedded systems, energy efficient, loop tiling, MLC PCM, write mode

Citation Format(s)

Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems. / Qiu, Keni; Li, Qingan; Hu, Jingtong; Zhang, Weigong; Xue, Chun Jason.

In: IEEE Transactions on Computers, Vol. 65, No. 7, 7273842, 01.07.2016, p. 2313-2324.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal