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Work-in-progress: A PV aware data placement scheme for read performance improvement on LDPC based flash memory

Research output: Chapters, Conference Papers, Creative and Literary WorksRGC 32 - Refereed conference paper (with host publication)peer-review

Abstract

This paper proposes to improve read performance of LDPC based flash memory by exploiting process variation (PV). The work includes three parts. First, a block grouping approach is proposed to classify the flash blocks based on their reliability. Second, based on the grouping approach, a read data placement scheme is proposed, which is designed to place read-hot data on flash blocks with high reliability. However, simply placing read-hot data to high reliable blocks conflicts with recent PV-aware wear leveling schemes. In the third part of the work, a grouping partition scheme is proposed to limit the number of high reliable blocks for read-hot data. In this case, read performance can be well improved with little impact on the lifetime improvement.
Original languageEnglish
Title of host publicationProceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion
PublisherAssociation for Computing Machinery
ISBN (Print)978-1-4503-5185-0
DOIs
Publication statusPublished - Oct 2017
Event12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES '17) - Seoul, Korea, Republic of
Duration: 15 Oct 201720 Oct 2017

Publication series

NameInternational Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS

Conference

Conference12th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES '17)
Abbreviated titleCODES+ISSS 2017
PlaceKorea, Republic of
CitySeoul
Period15/10/1720/10/17

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