WCET-Aware re-scheduling register allocation for real-time embedded systems with clustered VLIW Architecture

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Detail(s)

Original languageEnglish
Article number6414665
Pages (from-to)168-180
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number1
Publication statusPublished - Jan 2014

Abstract

Worst-case execution time (WCET) is one of the most important metric in real-time embedded system design. For embedded systems with clustered very long instruction word (VLIW) architecture, register allocation, instruction scheduling, and cluster assignment are three key activities for code optimization, which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem, i.e., independently performing register allocation, scheduling, and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled code. In this paper, a compiler level optimization, namely WCET-aware re-scheduling register allocation, is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling, and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 34% on average. © 1993-2012 IEEE.

Research Area(s)

  • Cluster assignment, graph coloring, instruction scheduling, register allocation, worst-case execution time (WCET)

Citation Format(s)

WCET-Aware re-scheduling register allocation for real-time embedded systems with clustered VLIW Architecture. / Huang, Yazhi; Shi, Liang; Li, Jianhua; Li, Qingan; Xue, Chun Jason.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 1, 6414665, 01.2014, p. 168-180.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review