VLSI implementation of computation efficient color image compression scheme based on adaptive decimation for portable device application

Adaptive Decimation can be applied to compress images with good visual quality and at low bit-rate, but involving floating point computation that requires the use of medium speed processors to achieve real time operation. A new approach proposed restructures the Adaptive Decimation algorithm, to a form using only a few simple arithmetic operations, which can be implemented with simple logical circuits. The encoder is practically free from complex numerical computation. Hardware implementation of the proposed algorithm was realized in FPGA. The architecture of the encoder is simple and suitable for applications in the development of low cost non-processor based portable device real time application. © 2009 Springer Science+Business Media, LLC.