TY - GEN
T1 - VLSI-implementable classically conditioned neural elements
AU - Nintunze, Novat
AU - Wu, Angus
AU - Chintrakulchai, Pichet
AU - Meador, Jack
PY - 1991
Y1 - 1991
N2 - Hardware implementation of the phenomena of classical conditioning is discussed. The circuits are built around a programmable floating gate synapse studied in earlier works and thought to be a part of an impulse neural network. Simulation results related to phenomena such as acquisition and its extinction, blocking and second order conditioning are presented. The methodology followed is that of using specialized cells. This method further allows the realization of phenomena currently under investigation such as facilitation, sensitization and habituation. Current research involves the use of pulse coded Hebbian laws in search of economical circuitry for VLSI implementation.
AB - Hardware implementation of the phenomena of classical conditioning is discussed. The circuits are built around a programmable floating gate synapse studied in earlier works and thought to be a part of an impulse neural network. Simulation results related to phenomena such as acquisition and its extinction, blocking and second order conditioning are presented. The methodology followed is that of using specialized cells. This method further allows the realization of phenomena currently under investigation such as facilitation, sensitization and habituation. Current research involves the use of pulse coded Hebbian laws in search of economical circuitry for VLSI implementation.
UR - https://www.scopus.com/pages/publications/0026393354
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0026393354&origin=recordpage
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 780300815
VL - 1
SP - 281
EP - 284
BT - Midwest Symposium on Circuits and Systems
PB - IEEE
T2 - 33rd Midwest Symposium on Circuits and Systems
Y2 - 12 August 1990 through 15 August 1990
ER -