TY - GEN
T1 - Triplet spike time dependent plasticity in a floating-gate synapse
AU - Gopalakrishnan, Roshan
AU - Basu, Arindam
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2015/7/27
Y1 - 2015/7/27
N2 - Synapses plays an important role of learning in a neural network; the learning rules which modify the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the compact implementation of a synapse using single floating-gate (FG) transistor (and two additional high voltage transistors) that can store a weight in a non-volatile manner and demonstrate the triplet STDP (T-STDP) learning rule developed to explain biologically observed plasticity. We describe a mathematical procedure to obtain control voltages for the FG device for T-STDP and also show measurement results, from a FG synapse fabricated in TSMC 0.35μm CMOS process to support the theory.
AB - Synapses plays an important role of learning in a neural network; the learning rules which modify the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the compact implementation of a synapse using single floating-gate (FG) transistor (and two additional high voltage transistors) that can store a weight in a non-volatile manner and demonstrate the triplet STDP (T-STDP) learning rule developed to explain biologically observed plasticity. We describe a mathematical procedure to obtain control voltages for the FG device for T-STDP and also show measurement results, from a FG synapse fabricated in TSMC 0.35μm CMOS process to support the theory.
UR - https://www.scopus.com/pages/publications/84946214443
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84946214443&origin=recordpage
U2 - 10.1109/ISCAS.2015.7168732
DO - 10.1109/ISCAS.2015.7168732
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781479983919
VL - 2015-July
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 710
EP - 713
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - IEEE
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -