Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

  • Kyuchul Chong
  • Xi Zhang
  • Daquan Huang
  • Mau-Chung Chang
  • Ya-Hong Xie

Detail(s)

Original languageEnglish
Pages (from-to)2440-2446
Journal / PublicationIEEE Transactions on Electron Devices
Volume52
Issue number11
Publication statusPublished - Nov 2005
Externally publishedYes

Abstract

A novel approach for three-dimensional substrate impedance engineering of p-/p+ Si substrate is described for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to radio frequency (RF) crosstalk via substrate and on-chip inductor performance. Electroless plating or electro-plating is used to fabricate Faraday cage for crosstalk isolation as well as to provide "true ground" contacts. A self-limiting porous Si (PS) formation process is employed to allow the insertion of PS regions from the backside of the wafer, eliminating completely the waste of chip surface area. On-chip inductors are situated above the semi-insulating PS regions allowing for greatly increased Q-factor and resonance frequency (fr). RF crosstalk is reduced to the level limited by that across the air gap between the measurement probes. © 2005 IEEE.

Research Area(s)

  • Crosstalk, Mixed-signal system-on-chip (SoC), On-chip inductor, Porous Si, Radio frequency (RF) isolation

Bibliographic Note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to lbscholars@cityu.edu.hk.

Citation Format(s)

Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC). / Chong, Kyuchul; Zhang, Xi; Tu, King-Ning; Huang, Daquan; Chang, Mau-Chung; Xie, Ya-Hong.

In: IEEE Transactions on Electron Devices, Vol. 52, No. 11, 11.2005, p. 2440-2446.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review