TY - GEN
T1 - Three-dimensional impedance engineering for mixed-signal system-on-chip applications
AU - Chong, Kyuchul
AU - Zhang, Xi
AU - Tu, King-Ning
AU - Huang, Daquan
AU - Chang, Mau-Chung Frank
AU - Xie, Ya-Hong
PY - 2005/9
Y1 - 2005/9
N2 - An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p-/p+ Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency. ©2005 IEEE.
AB - An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p-/p+ Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency. ©2005 IEEE.
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UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-33847132357&origin=recordpage
U2 - 10.1109/CICC.2005.1568757
DO - 10.1109/CICC.2005.1568757
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 0780390237
SN - 9780780390232
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 663
EP - 666
BT - Proceedings of the IEEE 2005 Custom Integrated Circuits Conference
PB - IEEE
T2 - 2005 IEEE Custom Integrated Circuits Conference (CICC 2005)
Y2 - 18 September 2005 through 21 September 2005
ER -