Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review
Author(s)
Related Research Unit(s)
Detail(s)
Original language | English |
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Article number | 5898389 |
Pages (from-to) | 1002-1004 |
Journal / Publication | IEEE Electron Device Letters |
Volume | 32 |
Issue number | 8 |
Publication status | Published - Aug 2011 |
Link(s)
Abstract
This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. © 2011 IEEE.
Research Area(s)
- High-κ gate dielectric, La2O 3, MOS, temperature dependence
Citation Format(s)
Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric. / Wong, Hei; Yang, B. L.; Kakushima, K. et al.
In: IEEE Electron Device Letters, Vol. 32, No. 8, 5898389, 08.2011, p. 1002-1004.
In: IEEE Electron Device Letters, Vol. 32, No. 8, 5898389, 08.2011, p. 1002-1004.
Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review