Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric

Hei Wong; B. L. Yang; K. Kakushima; Hiroshi Iwai

doi:10.1109/LED.2011.2157799

Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric

Hei Wong
, B. L. Yang
, K. Kakushima
, Hiroshi Iwai

Department of Electrical Engineering

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

13 Citations (Scopus)

Abstract

This letter reports the subthreshold characteristics of MOS transistors with the novel CeO₂/La₂O₃ stacked gate dielectric. We found that the top CeO₂ capping layer does not only improve the bulk properties of La₂O₃ by reducing the oxygen vacancies as a result of the reduction reaction of CeO₂ but also reduces the La₂O₃Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. © 2011 IEEE.

Original language	English
Article number	5898389
Pages (from-to)	1002-1004
Journal	IEEE Electron Device Letters
Volume	32
Issue number	8
DOIs	https://doi.org/10.1109/LED.2011.2157799
Publication status	Published - Aug 2011

Research Keywords

High-κ gate dielectric
La2O 3
MOS
temperature dependence

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title = "Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric",

abstract = "This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. {\textcopyright} 2011 IEEE.",

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AU - Wong, Hei

AU - Yang, B. L.

AU - Kakushima, K.

AU - Iwai, Hiroshi

PY - 2011/8

Y1 - 2011/8

N2 - This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. © 2011 IEEE.

AB - This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements. © 2011 IEEE.

KW - High-κ gate dielectric

KW - La2O 3

KW - MOS

KW - temperature dependence

UR - https://www.scopus.com/pages/publications/79960908460

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-79960908460&origin=recordpage

U2 - 10.1109/LED.2011.2157799

DO - 10.1109/LED.2011.2157799

M3 - RGC 21 - Publication in refereed journal

SN - 0741-3106

VL - 32

SP - 1002

EP - 1004

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 8

M1 - 5898389

ER -

Subthreshold characteristics of MOS transistors with CeO2La 2O3 stacked gate dielectric

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