Steady state direct current plasma immersion ion implantation (PIII) using a grounded conducting grid

A novel process to implant ions with a grounded conducting grid on top of the wafer stage is described. The implantation is performed in low gas pressure steady stale DC mode. The ion paths are numerical simulated by the particle-in-cell (PIC) method. It is observed that the ion paths are optimized for certain implant geometry. In this configuration, the directional angle of the acceleration vector does not depend on the mass and charge state of the ions and the ratio of the partial differentials of the scalar potential φ along the radial and longitudinal direction remains constant for different applied voltage. The retained dose and impact energy uniformity on the wafer is totally determined by the ratio of the radius of wafer stage r, the radius of chamber R, the distance between the wafer stage and the grid H, and the thickness of the wafer stage D. Our results suggest that the best ratio of r:R:H:D be 1:4:2.5:2, i.e., a disk shape chamber. In addition to retaining the large area and parallel processing advantages of plasma immersion ion implantation (PIII), the technique allows the implantation energy to be extended far beyond the limit of PIII as the technique obviates the use of the power modulator which not only limits the implantation energy but also is the most expensive and technologically complex hardware component in a PIII system.