Silicon wafer as a feasible candidate for tribological characterization of thin coatings under high contact stress?

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Article number204839
Journal / PublicationWear
Online published21 Mar 2023
Publication statusPublished - 15 Jul 2023


Silicon (Si) wafer is generally used as the substrate for structural analysis and residual stress measurement of thin coatings. A few studies can be found for mechanical and tribological characterization wherein Hertzian contact stress never exceeded 1 GPa. Si, being single crystal, pure, and having low surface roughness (Ra) is an ideal potential candidate for thin coating analysis. However, Si wafer breaks immediately under higher contact stress. The current study aims to push the contact stress limit to test thin coatings on Si wafer especially for friction and wear testing. To serve the purpose, different bias DLC coatings (−120 V, −80 V, −40 V, Zero V, +40 V, +80 V, +120 V) were deposited on Si wafer employing closed field unbalanced magnetron sputtering (CFUMS) system. Using conveniently available experimental approach, Hertzian contact stress in tribological tests has been pushed up to 2.6 GPa successfully on DLC coated Si wafer. Thus, it is feasible to test thin coatings on Si wafer at high contact stress which will provide useful and consistent friction and wear data such that further test using the steel substrate will be reduced by a significant margin. A thorough mechanical, tribological and structural (Raman) analysis is presented. It was found that −120 V possessed the highest hardness (H: 17.6 GPa), modulus (E: 184 GPa) and residual stress (4.5 GPa). The same coating produced the lowest sp2/sp3 ratio, wear rate using contact stress (0.092 × 10−13 mm4/N) and wear/friction energy (0.071 × 10−13 mm3/J2) in comparison to other coatings used in the study. Counter body analysis for −120 V shows the minimum scratch area depicting friction between transfer film and DLC hence the lowest coefficient of friction (0.061) was obtained. Moreover, surface topography is explained with the aid of atomic force microscope (AFM) images and surface roughness (Ra) data. AFM revealed craters and bumpy like surfaces for positive and negative biased samples respectively. © 2023 Elsevier B.V.

Research Area(s)

  • DLC, Hertzian contact stress, Silicon wafer, Tribology