Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Floating point division is a complex operation among all floating point arithmetic; it is also an area and a performance dominating unit. This paper presents double precision floating point division architectures on FPGA platforms. The designs are area optimized, running at higher clock speed, with less latency, and are fully pipelined. Proposed architectures are based on the well-known Taylor series expansion, using relatively smaller amount of hardware in terms of memory (initial look-up table), multiplier blocks, and slices. Two architectures have been presented with various trade-offs among area, memory and accuracy. Designs are based on the use of the partial block multipliers, in order to reduce hardware usage while minimizing the loss of accuracy. All the implementations have been targeted and optimized separately for different Xilinx FPGAs to exploit their specific resources efficiently. Compared to previously reported literature, the proposed architectures require less area, reduced latency, with the advantage of higher performance gain. The accuracy of the designs has been both theoretically analyzed and validated using random test cases.