Self-aligned process for single electron transistors

A fabrication technique for single electron transistors is presented. The charge island for the single electron transistor is confined in the z direction by two epitaxial layers serving as tunnel barriers and the lateral confinement in the x-y plane results from the dry etching of a source-drain pillar using an inductively coupled plasma source. The gate is deposited using a self-aligned process with the source contact serving as a shadow mask and separated from the conducting channel by a small gap for closed coupling of gate voltage, reduced leakage current, and high breakdown voltage (approximately -60 V). The designed and measured values of the tunnel resistance of the epitaxial layers were in good agreement. © 2001 American Vacuum Society.