Abstract
The increasing density and capacity of NAND flash memory leads to degraded reliability. To address the reliability issue, low-density parity-check code (LDPC) has been deployed in NAND flash memories due to its strong error correction capability. The drawback of LDPC is that, to correct data with high raw bit error rate (RBER), read latency will be amplified. To improve read performance, this paper proposes to apply lossless compression to reduce RBER on data pages. However, compression and decompression incur time overheads. Compressing all the data pages for RBER reduction will degrade write performance. In addition, the variation of compression ratio leads to variation of RBER reduction, thus varied read latency reduction. In this work, a selective data compression scheme is proposed for read performance improvement. Both read frequency and compression ratio of data are taken into consideration. Data in a flash page with high read frequency and good compressibility are prioritized for compression. Experimental results show that the proposed scheme can improve read performance by 42% on average, without impacting write performance.
Original language | English |
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Title of host publication | Proceedings |
Subtitle of host publication | 2018 IEEE 36th International Conference on Computer Design, ICCD 2018 |
Publisher | IEEE |
Pages | 43-50 |
ISBN (Electronic) | 978-1-5386-8477-1 |
DOIs | |
Publication status | Published - Oct 2018 |
Event | 36th IEEE International Conference on Computer Design, ICCD 2018 - Orlando, United States Duration: 7 Oct 2018 → 10 Oct 2018 https://www.iccd-conf.com/2018/Home.html |
Publication series
Name | IEEE International Conference on Computer Design, ICCD |
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Publisher | IEEE |
ISSN (Electronic) | 2576-6996 |
Conference
Conference | 36th IEEE International Conference on Computer Design, ICCD 2018 |
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Country/Territory | United States |
City | Orlando |
Period | 7/10/18 → 10/10/18 |
Internet address |
Research Keywords
- Compression
- LDPC
- NAND flash memory
- Read performance