Secure Integrated Circuit Design via Hybrid Cloud

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal

1 Scopus Citations
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Author(s)

Detail(s)

Original languageEnglish
Pages (from-to)1851-1864
Journal / PublicationIEEE Transactions on Parallel and Distributed Systems
Volume29
Issue number8
Online published20 Feb 2018
Publication statusPublished - 1 Aug 2018

Abstract

In order to ease the burden of the in-house integrated circuit (IC) design, cloud-based IC design platforms advance rapidly, bringing benefits such as reduced capital costs and convenient design collaboration. However, such migration raises security challenges on IC Intellectual Property (IP) protection. Sensitive design data is unwillingly exposed to the cloud. In this paper, we initiate the first study for secure cloud-based IC design, and propose a hybrid cloud framework for privacy-assured IC timing analysis, i.e., an expensive procedure in the IC design flow for circuit delay evaluation. Our key observation is that more and more IP blocks are universally reused. After carefully extracting a small portion of sensitive blocks from the circuit, our framework only outsources non-sensitive design data to the public cloud. However, that "data splitting" hinders sequential delay evaluation. We then develop algorithms to enable the public cloud to derive intermediate results from non-sensitive data, which can be integrated with sensitive data at the private cloud. Additionally, we devise a practical verification protocol to assure the integrity of outsourced computation. Security analysis shows that our design is resilient to IC reverse engineering. Evaluations over large IC benchmarks demonstrate its efficiency and effectiveness.

Research Area(s)

  • Cloud computing, Computation outsourcing, Delays, Hybrid cloud, Integrated circuits, IP networks, IP protection, Logic gates, Security

Citation Format(s)

Secure Integrated Circuit Design via Hybrid Cloud. / Yuan, Xingliang; Weng, Jian; Wang, Cong; Ren, Kui.

In: IEEE Transactions on Parallel and Distributed Systems, Vol. 29, No. 8, 01.08.2018, p. 1851-1864.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journal