Scheduling to optimize cache utilization for non-volatile main memories

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

11 Scopus Citations
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Author(s)

  • Jingtong Hu
  • Qingfeng Zhuge
  • Wei-Che Tseng
  • Shouzhen Gu
  • Edwin H.-M. Sha

Related Research Unit(s)

Detail(s)

Original languageEnglish
Article number6409835
Pages (from-to)2039-2051
Journal / PublicationIEEE Transactions on Computers
Volume63
Issue number8
Publication statusPublished - Aug 2014

Abstract

In power and size sensitive embedded systems, non-volatile memories (NVMs) are replacing DRAM as the main memory since they have higher density, lower static power consumption, and lower costs. Unfortunately, these technologies are limited by their endurance and long write latencies. To minimize the main memory access time and extend the lifetime of the NVM, we optimally schedule tasks by an ILP formulation. We also present a heuristic, Concatenation Scheduling, to solve large problems in a reasonable amount of time. Our experimental results show that when compared with list scheduling, concatenation scheduling can reduce the total memory access time by an average of 9.99% and increase the lifetime of the NVM by 26.66%. When compared with list scheduling, ILP can reduce the total memory access time by an average of 12.39% and increase the lifetime of the NVM by 38.74%. © 2013 IEEE.

Research Area(s)

  • Cache memories, memory management, primary memory, real-time and embedded systems

Citation Format(s)

Scheduling to optimize cache utilization for non-volatile main memories. / Hu, Jingtong; Zhuge, Qingfeng; Xue, Chun Jason; Tseng, Wei-Che; Gu, Shouzhen; Sha, Edwin H.-M.

In: IEEE Transactions on Computers, Vol. 63, No. 8, 6409835, 08.2014, p. 2039-2051.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review