Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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  • Nan Guan
  • Qingxu Deng
  • Zonghua Gu
  • Wenyao Xu
  • Ge Yu


Original languageEnglish
Article number56
Journal / PublicationACM Transactions on Design Automation of Electronic Systems
Issue number4
Publication statusPublished - 1 Sep 2008
Externally publishedYes


Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this article, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/nonpreemptive EDF scheduling, and compare the performance of different utilization bound tests. © 2008 ACM.

Research Area(s)

  • FPGA, Real-time scheduling, Reconfigurable devices

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