Sampled analog architecture for DCT and DST

Ashis Kumar Mal; Arindam Basu; Anindya Sundar Dhar

doi:10.1109/iscas.2004.1329399

Sampled analog architecture for DCT and DST

Ashis Kumar Mal
, Arindam Basu
, Anindya Sundar Dhar

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

9 Citations (Scopus)

Abstract

This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/iscas.2004.1329399
Publication status	Published - 2004
Externally published	Yes
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

Bibliographical note

Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

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title = "Sampled analog architecture for DCT and DST",

abstract = "This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.",

author = "Mal, \{Ashis Kumar\} and Arindam Basu and Dhar, \{Anindya Sundar\}",

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language = "English",

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T1 - Sampled analog architecture for DCT and DST

AU - Mal, Ashis Kumar

AU - Basu, Arindam

AU - Dhar, Anindya Sundar

N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

PY - 2004

Y1 - 2004

N2 - This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

AB - This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

UR - https://www.scopus.com/pages/publications/4344602912

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-4344602912&origin=recordpage

U2 - 10.1109/iscas.2004.1329399

DO - 10.1109/iscas.2004.1329399

M3 - RGC 21 - Publication in refereed journal

SN - 0271-4310

VL - 2

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

Sampled analog architecture for DCT and DST

Abstract

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