Sampled analog architecture for DCT and DST

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Original languageEnglish
Journal / PublicationProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2004
Externally publishedYes


Title2004 IEEE International Symposium on Cirquits and Systems - Proceedings
CityVancouver, BC
Period23 - 26 May 2004


This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

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