Sampled analog architecture for DCT and DST

Ashis Kumar Mal; Arindam Basu; Anindya Sundar Dhar

doi:10.1109/iscas.2004.1329399

Author(s)

Ashis Kumar Mal
Arindam Basu
Anindya Sundar Dhar

Detail(s)

Original language	English
Journal / Publication	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
Publication status	Published - 2004
Externally published	Yes

Conference

Title	2004 IEEE International Symposium on Cirquits and Systems - Proceedings
Place	Canada
City	Vancouver, BC
Period	23 - 26 May 2004

Link(s)

DOI	DOI https://doi.org/10.1109/iscas.2004.1329399 Final Published version
	Check@CityULib
Link to Scopus	https://www.scopus.com/record/display.uri?eid=2-s2.0-4344602912&origin=recordpage
Permanent Link	https://scholars.cityu.edu.hk/en/publications/publication(80d5609e-4a12-40c8-a3dd-c7e601749452).html

Abstract

This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/ subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

Bibliographic Note

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Citation Format(s)

[ RIS ] [ BibTeX ]

Sampled analog architecture for DCT and DST. / Mal, Ashis Kumar; Basu, Arindam; Dhar, Anindya Sundar.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004.

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

Mal, AK, Basu, A & Dhar, AS 2004, 'Sampled analog architecture for DCT and DST', Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2. https://doi.org/10.1109/iscas.2004.1329399

Mal, A. K., Basu, A., & Dhar, A. S. (2004). Sampled analog architecture for DCT and DST. Proceedings - IEEE International Symposium on Circuits and Systems, 2. https://doi.org/10.1109/iscas.2004.1329399

Mal AK, Basu A, Dhar AS. Sampled analog architecture for DCT and DST. Proceedings - IEEE International Symposium on Circuits and Systems. 2004;2. doi: 10.1109/iscas.2004.1329399

Mal, Ashis Kumar ; Basu, Arindam ; Dhar, Anindya Sundar. / Sampled analog architecture for DCT and DST. In: Proceedings - IEEE International Symposium on Circuits and Systems. 2004 ; Vol. 2.