Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

  • J. Zheng
  • Y. Han
  • B. Song
  • S. Dong
  • F. Ma
  • L. Zhong

Detail(s)

Original languageEnglish
Pages (from-to)1629-1630
Journal / PublicationElectronics Letters
Volume48
Issue number25
Publication statusPublished - 6 Dec 2012
Externally publishedYes

Abstract

A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 m, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this new structure, a high ESD failure current of 4.4 A was achieved with a total channel width of only 60 m. Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications. © 2012 The Institution of Engineering and Technology.

Citation Format(s)

Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection. / Zheng, J.; Han, Y.; Wong, H.; Song, B.; Dong, S.; Ma, F.; Zhong, L.

In: Electronics Letters, Vol. 48, No. 25, 06.12.2012, p. 1629-1630.

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review