TY - GEN
T1 - Register allocation for hybrid register architecture in nonvolatile processors
AU - Wang, Yiqun
AU - Jia, Hongyang
AU - Liu, Yongpan
AU - Li, Qing'An
AU - Xue, Chun Jason
AU - Yang, Huazhong
PY - 2014
Y1 - 2014
N2 - Nonvolatile processors (NVP) have been an emerging topic in recent years due to its zero standby power, data retention and instant-on features. The conventional full replacement architecture in NVP has drawbacks of large area overhead and high backup energy. This paper provides a partial replacement based hybrid register architecture to significantly abate above problems. However, the hybrid register architecture can induce potential critical data loss and backup errors. In this paper, we propose a critical-data overflow aware register allocation (CORA). Different from other register allocation methods, CORA efficiently reduces the possibility of critical data spilling and backup errors. The experiment results show that CORA reduces the critical data overflow rate by up to 52%. The hybrid register architecture reduces the chip area by 45.1% and backup energy by 82.8% when using CORA. © 2014 IEEE.
AB - Nonvolatile processors (NVP) have been an emerging topic in recent years due to its zero standby power, data retention and instant-on features. The conventional full replacement architecture in NVP has drawbacks of large area overhead and high backup energy. This paper provides a partial replacement based hybrid register architecture to significantly abate above problems. However, the hybrid register architecture can induce potential critical data loss and backup errors. In this paper, we propose a critical-data overflow aware register allocation (CORA). Different from other register allocation methods, CORA efficiently reduces the possibility of critical data spilling and backup errors. The experiment results show that CORA reduces the critical data overflow rate by up to 52%. The hybrid register architecture reduces the chip area by 45.1% and backup energy by 82.8% when using CORA. © 2014 IEEE.
UR - https://www.scopus.com/pages/publications/84907402177
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-84907402177&origin=recordpage
U2 - 10.1109/ISCAS.2014.6865319
DO - 10.1109/ISCAS.2014.6865319
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781479934324
SP - 1050
EP - 1053
BT - Proceedings - IEEE International Symposium on Circuits and Systems
PB - IEEE
T2 - 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014)
Y2 - 1 June 2014 through 5 June 2014
ER -