Refresh-aware loop scheduling for high performance low power volatile STT-RAM

Keni Qiu; Junpeng Luo; Zhiyao Gong; Weigong Zhang; Jing Wang; Yuanchao Xu; Tao Li; Chun Jason Xue

doi:10.1109/ICCD.2016.7753282

Refresh-aware loop scheduling for high performance low power volatile STT-RAM

Keni Qiu^*, Junpeng Luo, Zhiyao Gong, Weigong Zhang, Jing Wang, Yuanchao Xu, Tao Li, Chun Jason Xue

^*Corresponding author for this work

City University of Hong Kong

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

9 Citations (Scopus)

Abstract

The highlighted advantages of low leakage power, high storage density and immunity to electronic magnetic radiation make STT-RAM a promising candidate to build cache, SPM or main memory in embedded systems. However, write operations on STT-RAM have considerably longer latency and higher energy consumption than conventional SRAM. To solve this problem, researchers have proposed to relax STT-RAM's non-volatility and to have it work in a fast and low power mode. Under this volatile mode, refresh operations are needed to guarantee data correctness if their lifespan is larger than the retention time. It is observed that this refresh overhead is significant for data in stencil loops with the characteristic of constant read and write dependencies. This paper proposes a loop scheduling technique which can traverse loops in a new direction such that data lifespan can be greatly shortened. Therefore, overall refresh overhead can be efficiently mitigated so as to improve performance and reduce power consumption. The experimental results indicate that access latency and dynamic energy can be improved by 21.4∼96.0% and 22.0∼95.5% respectively by the proposed scheduling scheme.

Original language	English
Title of host publication	Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
Publisher	IEEE
Pages	209-216
ISBN (Print)	9781509051427
DOIs	https://doi.org/10.1109/ICCD.2016.7753282
Publication status	Published - 22 Nov 2016
Event	34th IEEE International Conference on Computer Design, ICCD 2016 - Scottsdale, United States Duration: 2 Oct 2016 → 5 Oct 2016

Publication series

Name	Proceedings IEEE International Conference on Computer Design
Publisher	IEEE
ISSN (Print)	1063-6404

Conference

Conference	34th IEEE International Conference on Computer Design, ICCD 2016
Place	United States
City	Scottsdale
Period	2/10/16 → 5/10/16

Funding

This work is supported by Beijing Advanced Innovation Center for Imaging Technology, China [Project No. 2014A030310344], the Project of Construction of Innovative Teams and Teacher Career Development for Universities and Colleges Under Beijing Municipality [Project No. IDHT20150507], National Natural Science Foundation of China [Project No. 61472260, 61402302 and 61502321]. Weigong Zhang is the corresponding author.

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Qiu, K., Luo, J., Gong, Z., Zhang, W., Wang, J., Xu, Y., Li, T., & Xue, C. J. (2016). Refresh-aware loop scheduling for high performance low power volatile STT-RAM. In Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016 (pp. 209-216). Article 7753282 (Proceedings IEEE International Conference on Computer Design). IEEE. https://doi.org/10.1109/ICCD.2016.7753282

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title = "Refresh-aware loop scheduling for high performance low power volatile STT-RAM",

abstract = "The highlighted advantages of low leakage power, high storage density and immunity to electronic magnetic radiation make STT-RAM a promising candidate to build cache, SPM or main memory in embedded systems. However, write operations on STT-RAM have considerably longer latency and higher energy consumption than conventional SRAM. To solve this problem, researchers have proposed to relax STT-RAM's non-volatility and to have it work in a fast and low power mode. Under this volatile mode, refresh operations are needed to guarantee data correctness if their lifespan is larger than the retention time. It is observed that this refresh overhead is significant for data in stencil loops with the characteristic of constant read and write dependencies. This paper proposes a loop scheduling technique which can traverse loops in a new direction such that data lifespan can be greatly shortened. Therefore, overall refresh overhead can be efficiently mitigated so as to improve performance and reduce power consumption. The experimental results indicate that access latency and dynamic energy can be improved by 21.4∼96.0% and 22.0∼95.5% respectively by the proposed scheduling scheme.",

author = "Keni Qiu and Junpeng Luo and Zhiyao Gong and Weigong Zhang and Jing Wang and Yuanchao Xu and Tao Li and Xue, {Chun Jason}",

year = "2016",

month = nov,

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doi = "10.1109/ICCD.2016.7753282",

language = "English",

isbn = "9781509051427",

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note = "34th IEEE International Conference on Computer Design, ICCD 2016 ; Conference date: 02-10-2016 Through 05-10-2016",

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Qiu, K, Luo, J, Gong, Z, Zhang, W, Wang, J, Xu, Y, Li, T & Xue, CJ 2016, Refresh-aware loop scheduling for high performance low power volatile STT-RAM. in Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016., 7753282, Proceedings IEEE International Conference on Computer Design, IEEE, pp. 209-216, 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, United States, 2/10/16. https://doi.org/10.1109/ICCD.2016.7753282

Refresh-aware loop scheduling for high performance low power volatile STT-RAM. / Qiu, Keni; Luo, Junpeng; Gong, Zhiyao et al.
Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. IEEE, 2016. p. 209-216 7753282 (Proceedings IEEE International Conference on Computer Design).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

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AU - Qiu, Keni

AU - Luo, Junpeng

AU - Gong, Zhiyao

AU - Zhang, Weigong

AU - Wang, Jing

AU - Xu, Yuanchao

AU - Li, Tao

AU - Xue, Chun Jason

PY - 2016/11/22

Y1 - 2016/11/22

N2 - The highlighted advantages of low leakage power, high storage density and immunity to electronic magnetic radiation make STT-RAM a promising candidate to build cache, SPM or main memory in embedded systems. However, write operations on STT-RAM have considerably longer latency and higher energy consumption than conventional SRAM. To solve this problem, researchers have proposed to relax STT-RAM's non-volatility and to have it work in a fast and low power mode. Under this volatile mode, refresh operations are needed to guarantee data correctness if their lifespan is larger than the retention time. It is observed that this refresh overhead is significant for data in stencil loops with the characteristic of constant read and write dependencies. This paper proposes a loop scheduling technique which can traverse loops in a new direction such that data lifespan can be greatly shortened. Therefore, overall refresh overhead can be efficiently mitigated so as to improve performance and reduce power consumption. The experimental results indicate that access latency and dynamic energy can be improved by 21.4∼96.0% and 22.0∼95.5% respectively by the proposed scheduling scheme.

AB - The highlighted advantages of low leakage power, high storage density and immunity to electronic magnetic radiation make STT-RAM a promising candidate to build cache, SPM or main memory in embedded systems. However, write operations on STT-RAM have considerably longer latency and higher energy consumption than conventional SRAM. To solve this problem, researchers have proposed to relax STT-RAM's non-volatility and to have it work in a fast and low power mode. Under this volatile mode, refresh operations are needed to guarantee data correctness if their lifespan is larger than the retention time. It is observed that this refresh overhead is significant for data in stencil loops with the characteristic of constant read and write dependencies. This paper proposes a loop scheduling technique which can traverse loops in a new direction such that data lifespan can be greatly shortened. Therefore, overall refresh overhead can be efficiently mitigated so as to improve performance and reduce power consumption. The experimental results indicate that access latency and dynamic energy can be improved by 21.4∼96.0% and 22.0∼95.5% respectively by the proposed scheduling scheme.

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ER -

Refresh-aware loop scheduling for high performance low power volatile STT-RAM

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