Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way

Research output: Journal Publications and Reviews (RGC: 21, 22, 62)21_Publication in refereed journalpeer-review

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Author(s)

Detail(s)

Original languageEnglish
Article number7331656
Pages (from-to)1808-1820
Journal / PublicationIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number5
Online published19 Nov 2015
Publication statusPublished - May 2016
Externally publishedYes

Abstract

As the endurance of flash memory keeps deteriorating, exploiting wear leveling (WL) techniques to improve the lifetime/endurance of flash memory has become a critical issue in the design of flash storage devices. Nevertheless, the deteriorated access performance of high-density flash memory makes the performance overheads introduced by WL non-negligible. In particular, the existing WL designs usually aggressively distribute the erases to all flash blocks evenly in a regular basis. As a result, a lot of non-negligible unnecessary data migrations would be imposed in the early stages of the device lifespan, and would be further exacerbated if a WL design selects improper victim blocks for erases. In contrast to the existing WL approaches, we propose a progressive WL design to perform WL in a progressive way to prevent any block from being worn out prematurely with minimized performance overheads caused by the unnecessary data migration. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed design. The results reveal that instead of sacrificing the device lifetime, performing WL in such a progressive way can not only minimize the performance overheads but also have potentials to extend the device lifetime.

Research Area(s)

  • Flash memory, flash storage device, multilevel cell (MLC), progressive, solid-state drive (SSD), storage systems, threshold, wear leveling (WL)

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