TY - GEN
T1 - Reduced Redundant Power Processing (R2P2) PFC Voltage Regulators
T2 - 31st IEEE Annual Power Electronics Specialists Conference (PESC '00)
AU - Tse, Chi K.
AU - Chow, Martin H.L.
AU - Cheung, Martin K.H.
PY - 2000/6
Y1 - 2000/6
N2 - High input power factor is becoming a mandatory requirement, in addition to tight output regulation, of dc power supplies that derive power directly from the ac mains. In principle, the power factor correction (PFC) and output regulation functions are separately achieved by two power stages. This paper addresses the amalgamation of the two power stages to form a PFC voltage regulator. The focus is the non-cascading structure that allows a higher overall efficiency to be achieved. Unlike the conventional cascade configuration, the circuits discussed in this paper allow part of the input power to be processed by only one stage, thereby reduce the amount of power redundantly processed by the two constituent power stages. This paper describes in particular a systematic synthesis method and some important issues related to the control of such converter circuits.
AB - High input power factor is becoming a mandatory requirement, in addition to tight output regulation, of dc power supplies that derive power directly from the ac mains. In principle, the power factor correction (PFC) and output regulation functions are separately achieved by two power stages. This paper addresses the amalgamation of the two power stages to form a PFC voltage regulator. The focus is the non-cascading structure that allows a higher overall efficiency to be achieved. Unlike the conventional cascade configuration, the circuits discussed in this paper allow part of the input power to be processed by only one stage, thereby reduce the amount of power redundantly processed by the two constituent power stages. This paper describes in particular a systematic synthesis method and some important issues related to the control of such converter circuits.
UR - https://www.scopus.com/pages/publications/0034472463
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-0034472463&origin=recordpage
U2 - 10.1109/pesc.2000.879921
DO - 10.1109/pesc.2000.879921
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 0780356926
VL - 2
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
SP - 825
EP - 830
BT - 2000 IEEE 31st Annual Power Electronics Specialists Conference
PB - IEEE
Y2 - 23 June 2000 through 23 June 2000
ER -