Reconfigurable RISC-V secure processor and SoC integration

Zhenya Zang; Yao Liu; Ray C. C. Cheung

doi:10.1109/ICIT.2019.8755206

Reconfigurable RISC-V secure processor and SoC integration

Zhenya Zang
, Yao Liu
, Ray C. C. Cheung

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

9 Citations (Scopus)

Abstract

In IoT (Internet of Things) applications, security issues are increasingly attracting attention. However, current embedded processors lack cryptographic protection mechanism. In this paper, an austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility. This core contains separate instructions and a data bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 board is taken as an architecture protocol verification platform, where the peak operating frequency of the RISC-V core and the encryption SoC is 105MHz and 111.5MHz, respectively. The hardware resource utilization is reduced compared with the MIPS core with identical efforts.

Original language	English
Title of host publication	Proceedings - 2019 IEEE International Conference on Industrial Technology (ICIT)
Publisher	IEEE
Pages	827-832
ISBN (Electronic)	9781538663769
ISBN (Print)	9781538663776
DOIs	https://doi.org/10.1109/ICIT.2019.8755206
Publication status	Published - Feb 2019
Event	The 20^th IEEE International Conference on Industrial Technology (ICIT 2019) - Melbourne, Australia Duration: 13 Feb 2019 → 15 Feb 2019 http://ieee-icit2019.org/

Publication series

Name	Proceedings of the IEEE International Conference on Industrial Technology
Volume	2019-February
ISSN (Print)	2641-0184
ISSN (Electronic)	2643-2978

Conference

Conference	The 20^th IEEE International Conference on Industrial Technology (ICIT 2019)
Abbreviated title	ICIT 2019
Place	Australia
City	Melbourne
Period	13/02/19 → 15/02/19
Internet address	http://ieee-icit2019.org/

Bibliographical note

Full text of this publication does not contain sufficient affiliation information. With consent from the author(s) concerned, the Research Unit(s) information for this record is based on the existing academic department affiliation of the author(s).

Research Keywords

RISC-V
Security processor
SoC
Wishbone

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10.1109/ICIT.2019.8755206

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Cite this

@inproceedings{d511ebba0fce4619a9f2aab738ed2eb6,

title = "Reconfigurable RISC-V secure processor and SoC integration",

abstract = "In IoT (Internet of Things) applications, security issues are increasingly attracting attention. However, current embedded processors lack cryptographic protection mechanism. In this paper, an austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility. This core contains separate instructions and a data bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 board is taken as an architecture protocol verification platform, where the peak operating frequency of the RISC-V core and the encryption SoC is 105MHz and 111.5MHz, respectively. The hardware resource utilization is reduced compared with the MIPS core with identical efforts.",

keywords = "RISC-V, Security processor, SoC, Wishbone",

author = "Zhenya Zang and Yao Liu and Cheung, \{Ray C. C.\}",

note = "Full text of this publication does not contain sufficient affiliation information. With consent from the author(s) concerned, the Research Unit(s) information for this record is based on the existing academic department affiliation of the author(s).; The 20<sup>th</sup> IEEE International Conference on Industrial Technology (ICIT 2019), ICIT 2019 ; Conference date: 13-02-2019 Through 15-02-2019",

year = "2019",

month = feb,

doi = "10.1109/ICIT.2019.8755206",

language = "English",

isbn = "9781538663776",

series = "Proceedings of the IEEE International Conference on Industrial Technology",

publisher = "IEEE",

pages = "827--832",

booktitle = "Proceedings - 2019 IEEE International Conference on Industrial Technology (ICIT)",

address = "United States",

url = "http://ieee-icit2019.org/",

}

Zang, Z, Liu, Y & Cheung, RCC 2019, Reconfigurable RISC-V secure processor and SoC integration. in Proceedings - 2019 IEEE International Conference on Industrial Technology (ICIT)., 8755206, Proceedings of the IEEE International Conference on Industrial Technology, vol. 2019-February, IEEE, pp. 827-832, The 20^th IEEE International Conference on Industrial Technology (ICIT 2019), Melbourne, Australia, 13/02/19. https://doi.org/10.1109/ICIT.2019.8755206

Reconfigurable RISC-V secure processor and SoC integration. / Zang, Zhenya; Liu, Yao ; Cheung, Ray C. C.
Proceedings - 2019 IEEE International Conference on Industrial Technology (ICIT). IEEE, 2019. p. 827-832 8755206 (Proceedings of the IEEE International Conference on Industrial Technology; Vol. 2019-February).

Research output: Chapters, Conference Papers, Creative and Literary Works › RGC 32 - Refereed conference paper (with host publication) › peer-review

TY - GEN

T1 - Reconfigurable RISC-V secure processor and SoC integration

AU - Zang, Zhenya

AU - Liu, Yao

AU - Cheung, Ray C. C.

N1 - Full text of this publication does not contain sufficient affiliation information. With consent from the author(s) concerned, the Research Unit(s) information for this record is based on the existing academic department affiliation of the author(s).

PY - 2019/2

Y1 - 2019/2

N2 - In IoT (Internet of Things) applications, security issues are increasingly attracting attention. However, current embedded processors lack cryptographic protection mechanism. In this paper, an austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility. This core contains separate instructions and a data bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 board is taken as an architecture protocol verification platform, where the peak operating frequency of the RISC-V core and the encryption SoC is 105MHz and 111.5MHz, respectively. The hardware resource utilization is reduced compared with the MIPS core with identical efforts.

AB - In IoT (Internet of Things) applications, security issues are increasingly attracting attention. However, current embedded processors lack cryptographic protection mechanism. In this paper, an austere RISC-V core processor with RV32I subset instruction is deemed as a master device to cooperate with an AES cryptographic engine in an SoC, due to its openness and flexibility. This core contains separate instructions and a data bus connected to a Wishbone crossbar. A Spartan-6 XC6SLX9 board is taken as an architecture protocol verification platform, where the peak operating frequency of the RISC-V core and the encryption SoC is 105MHz and 111.5MHz, respectively. The hardware resource utilization is reduced compared with the MIPS core with identical efforts.

KW - RISC-V

KW - Security processor

KW - SoC

KW - Wishbone

UR - https://www.scopus.com/pages/publications/85069039839

UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85069039839&origin=recordpage

U2 - 10.1109/ICIT.2019.8755206

DO - 10.1109/ICIT.2019.8755206

M3 - RGC 32 - Refereed conference paper (with host publication)

SN - 9781538663776

T3 - Proceedings of the IEEE International Conference on Industrial Technology

SP - 827

EP - 832

BT - Proceedings - 2019 IEEE International Conference on Industrial Technology (ICIT)

PB - IEEE

T2 - The 20<sup>th</sup> IEEE International Conference on Industrial Technology (ICIT 2019)

Y2 - 13 February 2019 through 15 February 2019

ER -

Reconfigurable RISC-V secure processor and SoC integration

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Research Keywords

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