TY - GEN
T1 - Reconfigurable acceleration for Monte Carlo based financial simulation
AU - Zhang, G. L.
AU - Leong, P. H W
AU - Ho, C. H.
AU - Tsoi, K. H.
AU - Lee, Dong-U
AU - Cheung, C. C C
AU - Cheung, R. C C
AU - Luk, W.
PY - 2005/12
Y1 - 2005/12
N2 - This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number system representation for determining the choice of number representation that meets numerical precision requirements. Our approach is then used in a complex financial engineering application, involving the Brace, Ga̧tarek and Musiela (BGM) interest rate model for pricing derivatives. We address, in our BGM model, several challenges including the generation of Gaussian distributed random numbers and pipelining of the MC simulation. Our BGM application, based on an off-the-shelf system with a Xilinx XC2VP30 device at 50 MHz, is over 25 times faster than software running on a 1.5 GHz Intel Pentium machine. © 2005 IEEE.
AB - This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrates its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture, which combines speed and flexibility by integrating a pipelined MC core with an on-chip instruction processor. We develop a generic number system representation for determining the choice of number representation that meets numerical precision requirements. Our approach is then used in a complex financial engineering application, involving the Brace, Ga̧tarek and Musiela (BGM) interest rate model for pricing derivatives. We address, in our BGM model, several challenges including the generation of Gaussian distributed random numbers and pipelining of the MC simulation. Our BGM application, based on an off-the-shelf system with a Xilinx XC2VP30 device at 50 MHz, is over 25 times faster than software running on a 1.5 GHz Intel Pentium machine. © 2005 IEEE.
UR - https://www.scopus.com/pages/publications/33846585053
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-33846585053&origin=recordpage
U2 - 10.1109/FPT.2005.1568549
DO - 10.1109/FPT.2005.1568549
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 0780394070
SN - 9780780394070
SP - 215
EP - 222
BT - Proceedings - 2005 IEEE International Conference on Field Programmable Technology
A2 - Brebner, Gordon
A2 - Chakraborty, Samarjit
A2 - Wong, Weng-Fai
PB - IEEE
T2 - 2005 IEEE International Conference on Field Programmable Technology
Y2 - 11 December 2005 through 14 December 2005
ER -