Real-time loop scheduling with leakage energy minimization for embedded VLIW DSP processors

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with host publication)peer-review

5 Scopus Citations
View graph of relations

Author(s)

Related Research Unit(s)

Detail(s)

Original languageEnglish
Title of host publicationProceedings - 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2007
Pages12-19
Publication statusPublished - 2007

Conference

Title13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007)
PlaceKorea, Republic of
CityDaegu
Period21 - 24 August 2007

Abstract

In this paper, we develop a novel real-time instruction-level loop scheduling technique to reduce leakage energy consumption for applications with loops on VLIW architecture. We first prove that the scheduling problem with the minimum leakage energy consumption within a timing constraint is NP-complete. Then, LEMLS (Leakage Energy Minimization Loop Scheduling) algorithm is designed to repeatedly regroup a loop based on rotation scheduling [3], and decrease leakage energy integrating with leakage power reduction mechanism. We conduct experiments on a set of DSP benchmarks based on the power model of the VLIW processors in [12]. The results show that our algorithm achieves significant leakage energy saving compared with list scheduling and the algorithm in [19]. © 2007 IEEE.

Citation Format(s)

Real-time loop scheduling with leakage energy minimization for embedded VLIW DSP processors. / Wang, Meng; Shao, Zili; Xue, Chun Jason et al.
Proceedings - 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2007. 2007. p. 12-19 4296831.

Research output: Chapters, Conference Papers, Creative and Literary Works (RGC: 12, 32, 41, 45)32_Refereed conference paper (with host publication)peer-review