TY - GEN
T1 - Real-time binocular stereo vision system based on FPGA
AU - Ma, Jiawei
AU - Yin, Wei
AU - Zuo, Chao
AU - Feng, Shijie
AU - Chen, Qian
N1 - Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].
PY - 2018
Y1 - 2018
N2 - Binocular stereo vision, as a typical technique of computer vision, is versatile in three-dimensional shape measurement. However, the efficiency and speed are limited by the inherent instruction cycle delay within traditional computers, leading to large quantities of image data and computational complexity. Consequently, this paper describes a real-time binocular stereo vision system based on FPGA implementation. Considering FPGA's parallel architecture, both in storing and calculating, the whole system is a full-pipeline design and synchronized with the identical system clock so that different parts of the stereo processing can work simultaneously to improve the processing speed. As the complete image processing framework contains rectification, stereo correspondence and the left-right consistency check is realized by only one FPGA chip without other external devices, making system highly integrated and low cost. To avoid unnecessary cost of the FPGA resource, the dual-camera calibration is done offline by MFC-based software while the intrinsic and extrinsic parameters are transmitted into the FPGA through system interaction. © 2018 SPIE.
AB - Binocular stereo vision, as a typical technique of computer vision, is versatile in three-dimensional shape measurement. However, the efficiency and speed are limited by the inherent instruction cycle delay within traditional computers, leading to large quantities of image data and computational complexity. Consequently, this paper describes a real-time binocular stereo vision system based on FPGA implementation. Considering FPGA's parallel architecture, both in storing and calculating, the whole system is a full-pipeline design and synchronized with the identical system clock so that different parts of the stereo processing can work simultaneously to improve the processing speed. As the complete image processing framework contains rectification, stereo correspondence and the left-right consistency check is realized by only one FPGA chip without other external devices, making system highly integrated and low cost. To avoid unnecessary cost of the FPGA resource, the dual-camera calibration is done offline by MFC-based software while the intrinsic and extrinsic parameters are transmitted into the FPGA through system interaction. © 2018 SPIE.
KW - Binocular Stereo Vision
KW - Depth Sensing
KW - FPGA
KW - Stereo Correspondence
UR - http://www.scopus.com/inward/record.url?scp=85051266019&partnerID=8YFLogxK
UR - https://www.scopus.com/record/pubmetrics.uri?eid=2-s2.0-85051266019&origin=recordpage
U2 - 10.1117/12.2500769
DO - 10.1117/12.2500769
M3 - RGC 32 - Refereed conference paper (with host publication)
SN - 9781510622562
VL - 10827
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Sixth International Conference on Optical and Photonic Engineering, icOPEN 2018
PB - SPIE - International Society for Optical Engineering
T2 - 6th International Conference on Optical and Photonic Engineering, icOPEN 2018
Y2 - 8 May 2018 through 11 May 2018
ER -