RASP 2.8: A new generation of floating-gate based field programmable analog array

Arindam Basu; Christopher M. Twigg; Stephen Brink; Paul Hasler; Csaba Petre; Shubha Ramakrishnan; Scott Koziol; Craig Schlottmann

doi:10.1109/CICC.2008.4672061

RASP 2.8: A new generation of floating-gate based field programmable analog array

Arindam Basu
, Christopher M. Twigg
, Stephen Brink
, Paul Hasler
, Csaba Petre
, Shubha Ramakrishnan
, Scott Koziol
, Craig Schlottmann

Research output: Journal Publications and Reviews › RGC 21 - Publication in refereed journal › peer-review

23 Citations (Scopus)

Abstract

The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks(CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth(> 50 MHz), accuracy(> 9 bits), dynamic range(> 7 decades of current), speed of floating-gate programming(> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented. © 2008 IEEE.

Original language	English
Article number	4672061
Pages (from-to)	213-216
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672061
Publication status	Published - 2008
Externally published	Yes
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: 21 Sept 2008 → 24 Sept 2008

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Publication details (e.g. title, author(s), publication statuses and dates) are captured on an “AS IS” and “AS AVAILABLE” basis at the time of record harvesting from the data source. Suggestions for further amendments or supplementary information can be sent to [email protected].

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title = "RASP 2.8: A new generation of floating-gate based field programmable analog array",

abstract = "The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks(CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth(> 50 MHz), accuracy(> 9 bits), dynamic range(> 7 decades of current), speed of floating-gate programming(> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented. {\textcopyright} 2008 IEEE.",

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AU - Basu, Arindam

AU - Twigg, Christopher M.

AU - Brink, Stephen

AU - Hasler, Paul

AU - Petre, Csaba

AU - Ramakrishnan, Shubha

AU - Koziol, Scott

AU - Schlottmann, Craig

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AB - The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks(CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth(> 50 MHz), accuracy(> 9 bits), dynamic range(> 7 decades of current), speed of floating-gate programming(> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented. © 2008 IEEE.

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M3 - RGC 21 - Publication in refereed journal

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JF - Proceedings of the Custom Integrated Circuits Conference

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RASP 2.8: A new generation of floating-gate based field programmable analog array

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